Stud Bumps Research Articles

Development of chip-on-flex using SBB flip-chip technology

A bare LSI chip mounted onto a flexible substrate is called chip-on-flex (COF). Companies and universities are desperately developing COF. In this paper, the development of COF using stud bump bonding (SBB) flip-chip technology will be introduced. So far, SBB technology has been adopted when ceramic or glass-epoxy is used as a substrate material for chip size packages (CSPs) and multi-chip modules (MCMs). Recently there is a great demand for developing SBB technology toward a flexible substrate. SBB technology needs to keep a flexible substrate flat during the assembly process. A flexible substrate was adhered to a flat carrier using a thermal release sheet in order to keep it flat. Since this thermal release sheet loses its adhesive strength by applying heat beyond 160°C, it is easy to peel off accomplished specimens from the flat carrier after assembling. SBB specimens were prepared using liquid crystal polymer (LCP) and polyimide (PI) as a flexible substrate. Reliability tests, such as pressure cooker test (PCT), thermal shock test (TST) and reflow soldering after moisture storage test, were carried out for these specimens. In PCT, both LCP and PI specimens passed as a result of using proper underfill for each substrate. In TST, both specimens also passed using the underfill selected in PCT. In reflow soldering after moisture storage test, LCP specimens passed, on the other hand PI specimens needed to be baked after moisture storage in order to pass the reflow.

Assembly issues in three flip chip processes

Discusses three simple and low‐cost flip chip assembly processes. First, flip chip on board using non‐conductive adhesive is evaluated. This process can give reasonable reliability and high assembly yield, when the parameters for epoxy placement and bonding are optimised. Second, the flip chip assembly process using reflowable no‐flow underfill is discussed. Because the underfill epoxy is already placed in the gap between the IC chip and the substrate before reflow, it is not easy to control the solder joints’ collapse and obtain the desired solder‐joint shapes and stand‐off distance during reflow. Finally, the stud bump bonding process is also discussed. It is not easy although possible to maintain the optimal dipping of the conductive adhesive, when the average height of the gold bumps is small. Some solutions for overcoming the above‐mentioned difficulties are presented in this paper.

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.

Single chip bumping and reliability for flip chip processes

Abstract Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.

ADHESIVE FLIP CHIP BONDING ON FLEXIBLE SUBSTRATES

Flip chip attachments provide the highest interconnection density possible — which makes this technology very attractive for use with flexible high density substrates. This technology stimulated the development of new interconnection techniques such as anisotropic conductive adhesives, isotropic conductive adhesives and non-conductive adhesives.This paper presents three approaches to a flip chip adhesive process based on flexible polyimide and polyester substrates using gold, nickel/gold and gold stud bumps. A promising candidate for adhesive joining technique are the isotropic conductive adhesives. These adhesives are isotropically conductive, which means that they conduct electricity equally in all directions. To use such adhesives in flip chip applications, the material must be applied precisely onto the points to be electrically connected, and must be not allowed to flow and short circuit between circuit lines. The anisotropically-conductive adhesive materials are prepared by dispersing electrically-conductive particles in an adhesive matrix at a concentration high enough to assure reliable conductivity between the substrate and the IC electrodes. Another possibility is the use of non-conductive adhesives and goldbumped chips, which are bonded via thermocompression to the substrate. During the bonding the bumps pierce through a non-conducting adhesive foil and make the electrical contact while the adhesive supplies the mechanical stability. Moreover, the adhesive fills the gap between chip and substrate, relieving the bumps of the mechanical stress resulting from the different CTEs.The reliability evaluation was performed with specific regard to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance as a function of temperature and humidity.

New optical and electrical hybrid packaging techniques using optical waveguides for optoelectronic multichip modules : Shinji Koike, Fusao Shimokawa, Tohru Matsurra and Hideyuki Takahara. IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 19 (1), 124 (1996)

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.