Stuck Open Research Articles

Performance Analysis of BIST Algorithms

Objective: Performance analyses of March LR and March C- are presented to achieve high fault coverage, low power dissipation, less area utilization and minimum testing time. Methods: Testing of memory consist of Built-In-Self-Test (BIST) controller and circuit-under-test. BIST algorithms are resided inside the BIST controller. BIST algorithms such as March LR and March C- are coded in term of finite state machine. Memory is modeled in verilog and simulated in ModelSims for testing memory faults and it is synthesized by using Xilinx Vivado 2012.2 EDA tool for power, area and timing analysis. Findings: Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique. Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are Stuck-At Fault (SAF), Stuck Open Fault (SOF), Transition Fault (TF), Coupling Fault (CF) etc. These functional faults are model and write the code in verilog. Faults are inserted and detected using ModelSims. Using Xilinx Vivado 2012.2 EDA tool, power, area and timing are analyzed. Comparison is made between March C- and march LR. Even though March LR has more length (14N), it has high fault coverage and lesser power dissipation. Thus, March LR is more efficient than March C-. Applications/Improvements: The fault coverage is improved by using March LR. More improvement in March LR can detect more faults which result in the efficiency for online BIST. Keywords: BIST Algorithm, Built-In-Self-Test (BIST), March C- and March LR, Memory Testing

Analysis of single failure criteria and operator action effect for different SGTR mitigation strategies of HPR1000

Establishment of a unified single failure criteria hypothesis and operator action for Steam Generator Tube Rupture (SGTR) accident in Deterministic Safety Analysis (DSA) is not an easy thing due to the complexity of the transient and the various operator actuations. Also, it’s very difficult to finish leakage in 30 min without operator action. In HPR1000 type nuclear power plant design, two kinds of mitigation strategy to cope with SG overfill risk and radioactive release risk can be adopted. In this paper, behavior of HPR1000 under different operator actions and single failure criteria hypothesis for this two mitigation measures were investigated. System response featured by primary pressure, SG level, break mass flow rate, safety injection mass flow rate was obtained to investigate single failure criteria and operator manual intervention effect. For strategy 1, if VDA stuck open was chosen as single failure criteria, primary loop would be over cooled and accumulator safety injection would increase with more drastically fluctuation. In strategy 2, AFW isolation failure was chosen as single failure criteria from SG overfill risk aspect. Affected SG would overfill if AFW isolation failure lasting over 5 min. Combined manual PRZR spray and SIS termination can obtain faster depressurization and leakage termination rate within controllable core boiling and acceptable radioactive release in strategy 1. However, in Strategy 2, manual PRZR spray depressurization and manual SIS termination have little effect on accident mitigation due to VDA comparatively large cooling ability and early intervention. From T-H safety aspect after SGTR, operator manual intervention has more obvious effect in strategy 1 than in strategy 2, which can provide multiple redundant engineered safety features.

Detection of Stuck Open and Short Fault in SRAM Based System

A novel scan-based Built-In Self-Test (BIST) architecture is designed with Low-Power (LP) for weighted pseudorandom test pattern generation (WPTPG) and reseeding, which is easy for the pseudorandom testing and deterministic BIST. The pseudorandom testing stage is designed by disabling a section of scan chains and in the deterministic BIST stage, the design-for-testability architecture is reorganize slightly while the linear-feedback shift register is kept short. The proposed technique of a BIST design for fault detection and fault diagnosis of Static-RAM (SRAM) based Field Programmable Gate Array (FPGAs) can detect the interconnect resources in the Configurable Logic Blocks (CLBs). The test pattern generator and output response analyzer are configured by CLBs in FPGAs. The testing procedure undergoes three major test blocks. They are Test Pattern Generator (TPG), Output Response Analyzer (ORA) and Block Under Test (BUT) in each test block. The stuck open and short faults are detected using SRAM based FPGA are observed in this paper.

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

A resistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor between two circuit nodes that should be connected. A stuck-open (SOP) defect is a complete break (no current flow) between two circuit nodes that should be connected. Conventional single stuck-at fault diagnosis cannot precisely diagnose these two defects because the test results of defective chips depend on the sequence of test patterns. This paper presents precise diagnosis techniques for these two defects. The diagnosis techniques take the test-pattern sequence into account, and therefore, produce precise diagnosis results. Also, our diagnosis technique handles multiple faults of different fault models. The diagnosis techniques are validated by experimental results. Twelve SOP and one resistive-open chips are diagnosed out of a total of 459 defective chips.

An Efficient Automatic Test Pattern Generator forStuck‐Open Faults in CMOS Combinational Circuits

In this paper, we describe a highly efficient automatic test pattern generator for stuck‐open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck‐at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.

Inerting and venting of mark II containments in BWR nuclear plants

An analysis of hydrogen control systems corroborates containment inerting as the only way of preventing hydrogen explosions which may jeopardize the integrity of BWR Mark II containments during severe accidents. A severe Large Break LOCA and a severe Stuck Open Relief Valve Accident are simulated by the MARCH 2.0 code to compare the advantages and disadvantages of pre-inerting and post-inerting, with or without venting, in BWR Mark II containments.