Test Generation For Stuck-at Faults Research Articles

Harzard-Based ATPG for Improving Delay Test Quality

Fault coverage is a popular test criterion in delay testing. In order to improve test coverage, an efficient automatic test pattern generation (ATPG) method especially aimed at hazard-based detection condition (HDC), referred to as HDC test generation, is proposed. The proposed method effectively enhances the testability of the faults which are undetectable under conventional detection conditions (CDC) but may fail the circuit in some special function operations. The necessity and feasibility of the hazard-based detection condition is analyzed. Using the improved traditional stuck-at fault test generation tool, we have implemented an efficient HDC test generation for transition delay fault. Experimental results on ISCAS'89 benchmark circuits demonstrate that the proposed HDC test generation can improve the fault converage by an average of 3.64 % for conventional LOS test and an average of 4.6 % for conventional LOC test.

I DDT: Fundamentals and test generation

It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed. This paper precisely defines the concept of average transient current (IDDT) of CMOS digital ICs, and experimentally analyzes the feasibility of IDDT test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions, which enables IDDT test generation at logic level. The Bayesian optimization algorithm is utilized for IDDT test generation. Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5, and likely to be IDDT testable. It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test. IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by using IDDT testing.

INCREDYBLE: A new search strategy for design automation problems with applications to testing

A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter (e.g., operand size), and indirectly, to random-logic circuits as well. Under the proposed approach, exhaustive search for an optimal solution is performed for small versions of the target circuit, obtained by scaling-down all the size parameters of the circuit (e.g., by reducing the operand size). The optimal solutions obtained for the small circuits are studied, and analytic rules are derived to capture their common features. Using these rules, the solutions are scaled-up into a high-quality solution for the large target circuit. The method, its feasibility and limitations are described in this work. The method is applied to two problems related to testing of digital circuits, namely, test generation for stuck-at faults and test generation for path delay faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computation of floating mode delay in combinational circuits: practice and implementation

Delay computation in combinational logic circuits is complicated by the existence of unsensitizable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but the authors use a recently developed single-vector condition, that is known to be necessary and sufficient for a path to be responsible for the delay of a circuit (i.e., true) in the floating delay model. They build on this theory and develop an efficient and correct delay computation algorithm, for the floating mode delay. The algorithm uses a technique called timed-test generation and can be incorporated into any stuck-at fault test generation framework. The authors describe in detail an implementation of the timed-test generation algorithm that uses both logical and timed forward/backward implication and backtrace procedures to simultaneously prove the truth or falsity of sets of paths in the circuit. Logical and temporal conflict detection during implication and backtrace are used to speed up the algorithm. Unlike previous techniques, the algorithm remains highly efficient: even when a large number of distinct gate and path delays exist in the given circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>