Abstract
It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed. This paper precisely defines the concept of average transient current (IDDT) of CMOS digital ICs, and experimentally analyzes the feasibility of IDDT test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions, which enables IDDT test generation at logic level. The Bayesian optimization algorithm is utilized for IDDT test generation. Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5, and likely to be IDDT testable. It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test. IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by using IDDT testing.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
