Stub Series Terminated Logic Research Articles

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Aim: This paper will focus on promoting the ideas of green communication Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication Objective: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication. Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs. Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm). Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

SSTL I/O Based Current Optimized Thermal Energy Efficient ROM Design on 28nm FPGA

In this work, energy efficient ROM is being designed using Kintex 7 which is able to scale down the circuit to 28 nm. For Testing the ROM compatibility, ROM is operated on operating frequencies (10GHz, 15GHz, 20GHz, 25GHz ) .Whenever capacitance is scaled down from 15pf to 5pf, there is I/O power and total power reduction but it is observed that there is no reduction in Clock power, and a very small reduction in leakage power. FPGA is an Integrated Circuit that comprises of input/output buffer, programmable interconnect structure and an array of configurable logic blocks, which featurisms fast prototyping and consumer configurability which gives the advantage of short turnaround time( i.e. time required from start of process till a functional chip is obtained).10MBits of on chip Memory is being provided on Xilinx FPGA in 36Kbits blocks, which supports dual port operation. Stub Series Terminated Logic (SSTL) is an Input/output standard which is selected because it avoids the transmission lie reflection and overall power dissipation. The purpose of Voltage scaling is to reduce leakage power. When capacitance of output load is scaled from 50pF to 5pF, there are 32-37% saving in I/O Power, 0-0.1% Leakage Power saving, there will be a 1-5% saving in Total Power. This design is implemented on Kintex-7 FPGA using Xilinx ISE & Verilog. The technique of Frequency Scaling has been used to reduce the leakage power consumption within the range of 80% to 44.8%, consumption in total power in range of 45.8% to 21.36% and the reduction in Junction temperature range is from 3.5% to 1.6% for 10GHz frequency.

SSTL I/O Standard Based Low Power Thermal Aware Vedic Multiplier Design on FPGA

This work is about designing of thermal aware low power Vedic multiplier using Stub-Series Terminated Logic (SSTL). The design of Vedic multiplier is a part of Vedic arithmetic circuits design project. “Urdhva-Tiryagbhyam” sutra is used to design the Vedic multiplier. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. When we use SSTL135_R in place of SSTL12, SSTL12_DCI, SSTL15, and SSTL135_DCI, there is 42.5%, 82.7%, 28.12%, and 72.9% reduction in I/O power at 21 0 C, 40 0 C, 53.5 0 C and 56.7 0 C. This design is implemented on Artix-7 FPGA using Verilog as hardware description language and Xilinx ISE 14.1 as simulator.

English

Stub-Series Terminated Logic (SSTL) IO standards and theory of Vedic Mathematics are used in design of Vedic multiplier. This vedic multiplier is a part of Vedic arithmetic circuits design project for Vedic Processor Design. This Vedic multiplier design is based on the formula “Urdhva-Tiryagbhyam” means Vertical and cross wise. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. There is 8.27% reduction in Total power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 14.19% reduction in IO power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 50% reduction in Total power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. There is 85.16% reduction in IO power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. This design is implemented on 28nm FPGA using Verilog and Xilinx Integrated System Environment 14.1. There is no change in Leakage power with change in IO standards. Leakage power depends on ambient temperature. In the other words, leakage power is directly proportional to ambient temperature. Keywords–SSTL, Low Power, Vedic Multiplier, IO Standard, FPGA

SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA

In this particular work, we have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA. We have used Xilinx ISE software development kit for all the observation done in this particular research work. Here, we have taken SSTL (StubSeries Terminated Logic) as input-output standard. We have considered six subcategories of SSTL (i.e. SSTL135, SSTL135_R, SSTL15, SSTL15_R, SSTL18_I and SSTL18_II) for four different WLAN frequencies (i.e. 2.4GHz, 3.6GHz, 4.9GHz, and 5.9GHz). We have done analysis considering five basic powers i.e. clock power, logic power, signal power, IOs power, leakage power and total power. There is 50-60% reduction in power dissipation, which is possible with proper selection of the most energy efficient IO standards i.e. SSTL135_R among SSTL logic families.

A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control

A 1GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032mm2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations.

A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about 50 Q, was implemented using a 70 nm 1-poly 3-metal DRAM process with a 1.5 V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface

This paper describes a validation system for an SLDRAM interface. The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style. The first technique is a source-synchronization scheme. Since the chip that transmits data also supplies the data clock, the clock and data are completely synchronous. The second is the timing vernier technique. A wait time for output data is programmable in each SLDRAM. Therefore, the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size. The validation chip is designed to emulate these operations. The chip is fabricated using a 0.35-/spl mu/m CMOS process technology and packaged in a conventional 0.65-mm pitch thin small out-line package, mounted on a single-chip module, and put into an eight-module system. A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals. From system-level measurements, the data eye width of 600 ps is obtained at a data rate of 600 Mbps. Errorless data transmission is observed in both read and write operations in a bit-error rate testing. The validation system has successfully demonstrated a data-transmission rate of 1.2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2.5 V.