Thin-film Transistor Structure Research Articles

High capacity organic memory structures based on PVP as the insulating layer

The electrical behaviour of organic memory structures based on gold nanoparticles (AuNPs) and poly 4-vinylphenol as the gate dielectric are reported in this work. Metal–insulator–semiconductor (MIS) and thin film transistor structures were used to fabricate the control and memory devices. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of AuNps embedded within the insulating layer were used as the floating gate. All memory devices exhibited clear hysteresis in their electrical characteristics [capacitance–voltage (C–V) for MIS structures as well as output and transfer characteristics for transistors]. Both structures were shown to produce reliable and large memory windows by virtue of high capacity. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics as well as flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the AuNPs floating gate. Memory window of 38 V was achieved by scanning the applied voltage of the MIS structure between 40 and − 40 V. Similarly, a memory window of 27 V was achieved for the TFT-based memory structure. Under an appropriate gate bias of 1 s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 5 V resulted in a clear write and erase states.

Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With Compact Modeling

Zinc oxide thin-film transistors (TFTs) with different device geometries and source/drain (S/D) contact metallizations are investigated. To facilitate the analysis, the channel and contact regions in top-gated staggered and drain-offset TFTs employing various permutations of ruthenium (Ru) and gold (Au) bottom electrodes are quantified with a TFT device model. The staggered TFT structure employs identical geometric overlaps between the gate-and-S/D electrodes; whereas the drain-offset TFT structure replaces the gate-to-drain overlap with a geometric gap in the channel. First, the experimental TFT current–voltage ( ${I}$ – ${V}$ ) characteristics are disentangled into the intrinsic channel and contact components by the transmission line method. The contact and channel behaviors are then individually modeled using a universal transistor compact model. From evaluating the model parameters, the diverse device characteristics observed in this paper are attributed to the Au electrode’s electron doping effect altering the properties of both the TFT’s contact and channel regions.

Bottom-Metal Induced Leakage Current of LTPS Diode for ESD Protection

Leakage current behavior was investigated for diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in display product with high luminance backlight system. In this study, the bottom metal layer was adopted to suppress leakage current caused by light coming from backlight system. Different off-current behavior as each other electrical connection of metal layer was observed, source-contacted or floating bottom metal showed the high leakage current by increasing current flow through back-channel at off states while gate-contacted bottom metal have comparable low leakage current with non-bottom metal layer. This leakage current characteristic was verified by technology computer-aided design (TCAD) simulation. Objectives and Background A low temperature polycrystalline silicon (LTPS) have been widely used for in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode displays (AMOLEDs) as thin film transistor (TFT) backplane and system on panel (SOP), combined with controller, memory, and driver circuits, due to excellent electrical characteristics. The LTPS TFT based displays can achieve high brightness, high aperture ratio, high resolution, and low power consumption due to excellent electrical characteristics. On the other hand, in display product with high luminance backlight system, such as auto and mobile products, the LTPS TFTs require a bottom metal layer to reduce leakage current caused by light coming from backlight unit (BLU). This bottom metal layer in contacted with gate or source electrodes is applied under the poly-Si layer. However, this bottom metal layer may also affect seriously the leakage current of diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in SOP. In this study, the leakage current of LTPS diode for ESD protection was investigated with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. We measured the electrical characteristics with variation of electrical connection of bottom metal layer. Also, the technology computer-aided design (TCAD) simulation was performed to analyze the physical mechanism. From analysis results, optimized bottom metal design of LTPS diode was proposed for ESD production. Experiment Figure 1 shows the top-gate coplanar n-channel LTPS TFT structure with bottom metal layer under poly-Si. Gate and Drain electrodes were connected to common electrode in LTPS TFTs structure for LTPS diode. This LTPS diode was fabricated at low temperature of less than 450°C on glass substrate. The standard commercial NMOS processes, including the ion implantation, the excimer laser annealing (ELA), and the rapid thermal annealing (RTA), were employed in this experiment. To observe the electrical characteristics of LTPS diode, I-V characteristics were measured by using an Agilent B1500A semiconductor analyzer at room temperature. Results and Discussion Figure 2 shows I-V characteristics of LTPS diodes with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. The leakage current with source-contacted and floating bottom metal increased considerably compared with non-bottom metal. Especially, the leakage current with source-contacted bottom metal increased more than with floating bottom metal. On the other hand, the leakage current with gate-contacted bottom metal was low enough to be comparable with non-bottom metal. To analyze this phenomenon, we observed the electron concentration distribution within poly-Si at VGS= 0V, 10V, and -10V region using technology computer-aided design (TCAD) simulation as shown figure 3. For source-contacted bottom metal and floating bottom metal, at VGS= -10V, the electron was accumulated in the back-channel of poly-Si since the positive voltage is applied to back-channel by voltage difference between drain and bottom metal even though drain (=gate) electrode is applied to negative voltage. Therefore, at VGS= -10V, the leakage current flows through the back-channel in LTPS diodes with source-contacted bottom metal and floating bottom metal. But, for LTPS diode with gate-contacted bottom metal, when drain electrode was applied to negative voltage, there is no different voltage bottom metal and gate electrode because these electrodes were linked in common. Therefore, LTPS diode with gate-contacted bottom metal has low leakage current as comparable with non-bottom metal. Conclusion In summary, the leakage current of LTPS diode was strongly dependent on electrical connection of bottom metal layer. The electrical connection of bottom metal affects back-channel region within poly-Si due to the difference between bottom metal and drain electrodes at off region. Especially, LTPS diode with source-contacted bottom metal and floating bottom metal increased considerably the leakage current, while, gate-contacted bottom metal decreased leakage current. Therefore, bottom metal layer should be connected by gate electrode in LTPS diode for ESD protection. Figure 1

(Invited) Depth Analysis of Near Valence Band Maximum Defect States in Amorphous Oxide Semiconductors: Amorphous in-Ga-Zn-O

Since the thin film transistors (TFTs) using amorphous oxide semiconductor (AOS) was firstly reported in 2004[1], amorphous In–Ga–Zn–O (a-IGZO) have been studied intensively because they have large advantageous features such as large electron mobilities (larger than 10 cm2/Vs), small subthreshold voltage swing, and low temperature fabrication process [2,3]. A-IGZO with the nominal chemical composition of In:Ga:Zn=1:1:1 is now commercialized for liquid crystal displays (LCDs) for smart phone or high-resolution TV and large-size organic light-emitting diode displays, etc.. Although the a-IGZO TFTs are already commercialized, stability is still a critical issue if we use it for next generation display such as transparent or flexible. In particular, it is recognized that the negative shift of the threshold voltage (V th) is associated with the excitation of subgap photons from deep-energy defects just above the valence band maximum (called near-VBM defects), which was firstly found by hard X-ray photoemission spectroscopy (HAXPES) [4]. We recently reported that a-IGZO deposited at room temperature has large film-density-distribution in the depth direction [5]. In this study, we measured depth profile of near-VBM states including IGZO/substrate interface. It is important to understand the depth distribution also of defect density, because mobile electrons in field-effect device are induced at vicinity of substrate in case of bottom gate TFT structure. Although depth analysis was already reported for a-IGZO deposited by pulsed laser deposition (PLD), we report for a-IGZO deposited by sputtering method which is standardly used in mass-production process. As a result, we found that the depth profile is different between PLD and sputtering method. We used radio-frequency (RF) magnetron sputtering to deposit a-IGZO films on Si wafer with 150 nm SiO2 at room temperature. RF power, oxygen flow rate ratio (Ar:O2), deposition pressure were fixed at 70 W, 97:3 and 0.55 Pa, respectively. HAXPES measurements were carried out at BL15XU undulator beamline (hv = 6 keV) in SPring-8. Film thickness dependences were observed for 5 – 100 nm a-IGZO films. For extracting buried spectra, we used total reflection X-ray to modify the penetration depth [6]. From thickness dependence of VB spectra, we found that the near-VBM defect density increase with decreasing film thickness. It may suggest that a-IGZO at the vicinity of substrate has large defect density compared to bulk region. To separate the effect of surface and buried region, we extracted the buried spectra using total reflection of X-ray in HAXPES measurement and difference method. We successfully observed the depth profile in wide range from 0 to 100 nm and found that the defect density at the vicinity of substrate is several times higher than that at thick enough region. We will discuss more details including the relationship between the microstructure and near-VBM defects at the conference.

Vertical Channel a-IGZO Thin Film Transistors Using Thin Gate Dielectric

Oxide thin film transistors (TFTs) are widely used as backplane for displays such as active matrix organic light emitting diode display and active matrix liquid crystal display. And also, it can be used in many applications such as sensor and wearable devices which require small power consumption. For low power consumption, the operation voltage should be decreased and the vertical structure TFT is a candidate due to short channel length. In this study, we proposed a vertical structure TFTs using a thin gate dielectric. In this experiment, a vertical structure TFTs with a channel formed on the vertical sidewall of the gate electrode and a channel length controlled by the thickness of the gate electrode is proposed. The channel length was adjusted by the thickness of the gate electrode in the vertical TFTs developed in this paper. Figure 1 shows the fabricated vertical a-IGZO TFT developed in this study. This vertical TFTs has the feature of controlling the channel length by the thickness of the gate electrode and can achieve short channel length easily, which is useful for low driving voltage. To reduce the gate voltage also, the thin gate dielectric was used. Since the very thin gate insulator was used, low threshold voltage was obtained, and low voltage driving was possible. Figure 1

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing the Low-Temperature Polycrystalline-Si (LTPS) as their active areas are very crucial for the system-on-glass (SOG). The liquid-crystal display (LCD) or organic light emitting diode display are fabricated in the display area and their controls are performed by the micro-computer that is formed in the peripheral area. The application of high-performance poly-Si TFTs to the high-definition LCD light valves for projectors was reported for the first time[1]. Therefore, the requirements for the recrystallized Si film are a high quality, a large grain formation and a position control of the nucleation. To satisfy those requirements, a super lateral growth (SLG)[2] using the excimer laser annealing (ELA), a phase-modulated ELA[3], a solid-phase crystallization followed by ELA[1], a low-temperature solid-phase excimer laser crystallization[4], a Pd:YAG laser crystallization[5], a soft X-ray crystallization (SXC)[6] have been studied. For the device structure, the double gate TFT[7] and the tunnel TFT[8] have been developed. In our group, the low-temperature crystallization methods and the novel TFT utilizing tunnel effect have been researched. Low-temperature crystallization: For the ELA method, the mechanism of multi-pulse ELA crystallization has been clarified and a large grained film with a high-quality[4] was provided. In addition, hydrogens in a-Si film greatly influenced the crystallinity and grain size of the poly-Si[9,10] and we discovered the advantage in ELA of hydrogen–modulation-doped a-Silicon Layer[11]. For the SXC, a low-temperature crystallization of a-Si, Ge and SixGe1-x film was researched and developed using the short undulator as a light source. The fundamental process of the SXC-method is a local excitation of core electrons to vacuum level by photons followed by the atom movement due to the Coulomb repulsion, which results in the lower temperature process. The SXC-method reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x film by 100 - 150 degree C as compared with the conv. thermal crystallization. Novel TFT: Although the high-performance TFT with the high carrier mobility and low leakage current utilizing the large single crystalline grains has been intensively researched, it does not successfully operates from the productive viewpoint[12]. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated in a bottom-gate structure. Using a 1.7-nm-thick SiNx film, it reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect as shown in Fig.1[13]. It is considered that the fixed charge in the SiNx film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion. We conclude that TDTFT will suitable as a candidate of the next generation TFT structure.

Physical origin of the non-linearity in amorphous In-Ga-Zn-O thin-film transistor current-voltage characteristics

The amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) current – voltage (I-V) characteristics can be significantly distorted by either series resistance, RS, associated with the source/drain (S/D) contact regions or/and density of states. To isolate Rs contribution we used the five terminals coplanar homojunction TFT structure. Experimental results have shown this device structure has a low S/D contact resistance that do not contribute to observed I-V nonlinearity. We have shown using combination of the experimental data and two- dimensional simulations that the observed nonlinearity can be associated with the conduction band-tail states.

Reduced Mechanical Strain in Bendable a-IGZO TFTs Under Dual-Gate Driving

We report the reduced strain in bendable amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) with dual-gate (DG) driving. The performance of the fabricated TFTs on a 15- $\mu \text{m}$ polyimide substrate are sensitive to bending radius and the changes in threshold voltage ( $\Delta \mathrm {V}_{\mathrm {TH}}$ ) fits well by analytical modeling. DG driving TFTs are found very stable under tensile strain ( $\varepsilon$ ) compared with single-gate (SG) TFTs. Technology computer-aided design strain distribution confirms a 25% less strain on a-IGZO layer for DG TFT structure compared with SG TFT and the maximum tensile strain is observed at the center of the TFT channel. The SG and DG TFTs under 1 mm radius exhibit $\Delta \mathrm {V}_{\mathrm {TH}}$ (V) shift of −1.5 and −0.3 V, respectively, from the flat state, which is due to the reduced strain in the DG TFT.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

53‐2: Development of Cu BCE‐structure IGZO TFT for High‐ppi 85‐in. 8K x 4K 120Hz GOA LCD

The electrical characteristics of back‐channel‐etched (BCE)‐structure indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistors (TFTs) were studied. Through modifying the passivation layer and optimizing the selection of color‐filter material and the design of the gate‐driver‐on‐array (GOA) TFT structure, the GOA TFTs were made to exhibit good device reliability. Finally, a high‐performance 85‐in. 8K x 4K 120Hz GOA LCD was demonstrated.

(Invited) Thermoelectric Properties of π-Conjugated Polymers in Ionic-Liquid-Gated Transistors

Thermal energy havesting from low-temperature heat sources, such as human body, is a promissing method to feed energy to vast number of micro-devices and sensors in Internet of Things (IoT) technologies. Thermoelectric generator, used for this purpose, can directly convert heat into electric power through Seebeck effect. In recent years, organic semiconductor materials, such as π-conjugated polymers, have been attracting much attention as a potential candidate for light-weight, flexible, and low-toxic thermoelectric generators. However, thermoelectric performance of polymer-based devices are still low compared to that of inorganic materials, although various novel polymers exhibitting high mobilities have been synthesized so far. The possible reason for this is the absence of both the suitable doping method and the fundamental understanding of thermoelectric properties in these polymer materials. In general, the power factor (P) of a thermoelectric device is described as a product of the electrical conductivity (σ) and Seebeck coefficient (S) as P=S2σ, whereas these two quantities tend to show opposite behavior upon carrier doping. Thus, it is indispensable to clarify the accurate relationship between σ and S in doped films in order to obtain a guideline to improve P. In semicrystalline polymers such as PBTTT (Fig. 1(a)), an empirical relation of S∝σ -1/4 (P∝σ 1/2) has been reported in a wide range of σ by using chemical doping, although no physical background for this relation has been clarified [1]. However, different σ-S relation has also been pointed out recently based on the data analyses of various reports including the same data set in ref. 1 [2]. Such difference seems to arise from the different doping conditions in chemical doping. In this presentation, we report our recent challenge to determine the accurate σ-S relation in various high-mobility polymer materials by using an electrolyte-gated thin-film transistor (TFT) structure, which enables a continuous electrochemical doping on the same device up to high carrier densities. Fig. 1(b) shows a schematic illustration of the TFT device and measurement setup [3]. We adopted an ionic liquid as the electrolyte, which was drop-casted on the polymer thin film fabricated on the glass substrate. A temperature gradient was given by a couple of Peltier devices and the induced voltage (ΔV) and temperature difference (ΔT) between source (S) and drain (D) electrodes were measured to obtain seebeck coefficient (S=ΔV/ΔT) under various gate voltages (V g). The electrical conductivity was simultaneously measured at each V g. Fig. 1(c) shows an example of σ-S and σ-P relations upon electrochemical doping obtained for two PBTTT devices. We observe highly reproducible data for these devices. In the low conductivity region (σ<100 S/cm), the empirical relation of S∝σ -1/4 is clearly confirmed, whereas the deviation from this relation becomes evident in the high conductivity region (σ>100 S/cm). The maximum of P appears around the boundary of low and high conductivity regions. In the high conductivity region, the σ-S relation seems to approach S∝σ -1, typical to the Mott’s relation expected for metals. This behavior is consistent with the semiconductor-metal transition of PBTTT occuring at highly-doped regions, which is observed from the temperature dependence of the conductivity as well as the electron spin resonance (ESR) measurements. Similar σ-S relation was commonly observed in a wide range of polymers such as donor-acceptor (DA) type copolymers. The maximum value of P can be enhanced by the surface treatment of the substrate by self-assembled monolayers or by aligning the polymer main chain, presumably due to the increase of the mobility, although the S∝σ -1/4 relation is unchanged in the low conductivity regions. The above σ-S relation insensitive to the mobility is indicative of the contribution of domain boundaries in thermoelectric properties. [1] A. M. Glaudell et al., Adv. Energy Mater. 5, 1401072 (2015). [2] S. D. Kang et al., Nat. Mater. 16, 252 (2017). [3] J. Pu et al., Phys. Rev. B. 94, 014312 (2016). Figure 1

P-6.6: Fabrication of Cu BCE-structure IGZO TFTs for 85-inch 8K4K 120Hz GOA LCD Display

The electrical characteristics of the back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) were studied. The passivation layer ,the selection of color filter material and design of GOA TFT structure were modified for lessening the influence of H2O molecules adsorbing on the back channel of the BCE-structure. The negative and positive bias temperature stress results revealed that the optimized GOA TFTs exhibited good device reliability. Finally, a high performance 85-inch 8K4K 120Hz GOA LCD was demonstrated.

Circular electrodes to reduce the current variation of OTFTs with the drop-casted semiconducting layer

Circular organic thin film transistor (OTFT) structures are proposed to reduce the impact of variable grain alignment on the drive current of the polycrystalline organic thin film transistor (OTFT). As the circular structure is planar symmetric, the orientation of the grain cannot affect the drive current of the circular OTFT. Thus, circular electrodes expected to provide a lower variation. Top-gate, bottom-contact circular and conventional OTFTs with drop-casted polycrystalline 6,13-Bis(triisopropyl-silylethynyl) (TIPS)-Pentacene organic semiconducting layer (OSC) are fabricated to verify the theoretical variation reduction. The relative standard deviation (RSD), defined as the ratio of standard deviation and the average of drive current is used as the degree of variations in different structures. According to our fabrication result, circular transistors have a significantly lower variation (20% RSD), compared to the variation of conventional OTFTs (61% RSD).

High-Performance Recessed-Channel Germanium Thin-Film Transistors via Excimer Laser Crystallization

This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grains with a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from un-melted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect hole mobility of 447 cm2V−1s−1 with minor performance deviation.

Vertically Integrated Optical Sensor With Photoconductive Gain &gt; 10 and Fill Factor &gt; 70%

A hybrid active pixel optical sensor for high-resolution and high-sensitivity imaging is proposed and experimentally demonstrated. The sensor vertically integrates an amorphous silicon p-i-n photodiode and a low-temperature polycrystalline silicon readout thin-film transistor (TFT). The vertical integration results in a high fill factor (>70%) and an enlarged photosensing area in the pixel. In the photodiode-gated TFT structure of the sensor, the output current is amplified by operating the TFT in the sub-threshold regime. A weak wavelength-dependent photoconductive gain >10 is obtained at visible wavelengths, enabling large area low-level light detection.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlOx top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

PANI/ZnO Hybrid Nanocomposites TFT for NAND Gate Application

Thin Film Transistor (TFT) is the key element for future day’s electronic circuit, in which low cost, low temperature, vacuum free process and flexibility of the substrate are the need for the day. With Cellulose acetate substrate as an insulator layer for the TFT, the C-V characteristic had been performed to find the dielectric constant. Polyaniline (PANI) is doped with Zinc Oxide (ZnO), and these Nanocomposites are coated on the substrate. The structure of TFT is achieved by coating electrodes on PANI/ZnO layer and substrate. Study was done on this hybrid structure for its electrical characteristics such as mobility and resistivity. The surface roughness and morphology of PANI/ZnO were characterized by Atomic Force Microscope (AFM) and Scanning Electronic Microscope (SEM). The input and output characteristics of TFT was obtained using I-V measurement system. One of the basic building blocks of digital circuits is NAND gate. The NAND gate is designed, fabricated and tested for its output voltage.

Self-Aligned Amorphous Indium-Tin-Zinc-Oxide Thin Film Transistors on Polyimide Foil

In this work, we report on high-performance coplanar self-aligned (SA) amorphous-Indium-Tin-Zinc-Oxide (a-ITZO) thin-film transistors (TFTs) on flexible polyimide substrate. The a-ITZO films are first optimized with respect to the oxygen ratio, thickness and final anneal conditions with common-gate TFTs structure on Si/SiO2 substrate. Optimized TFTs show mobility (μlin) between 20.0–25.0 cm2/(V.s). Material characterization revealed some degree of order compared to a truly amorphous film like a-IGZO but no grain boundaries or crystalline domains were observed. The a-ITZO films were integrated in coplanar SA TFT architecture on polyimide using hydrogen rich plasma (SiH4 based chemistry) as dopant for the source/drain (S/D) regions resulting in field-effect mobility (μFE) of 27.0 cm2/ (V.s), sub-threshold slope (SS−1) of 0.40 V/decade and ION /IOFF ratio of >108. The threshold voltage shifts of the TFTs under both positive and negative gate bias stress of 1MV/cm for 104 seconds were less than 1.5 V. We have also investigated the applicability of the SA a-ITZO TFTs in logic circuitry such as 19-stage ring-oscillators (ROs).

Interface engineering with double-network dielectric structure for flexible organic thin film transistors

Abstract Taking inspiration from the characteristics and the limitations of flexible organic thin-film transistor (OTFT) devices, a novel surface modification method was proposed to modify the gate insulator to tune the mechanical compatibility and adhesion energy between gate insulator and semiconductor layer for high performance flexible OTFT devices. The surface modification method aimed to form a polymer network structure within the cross-linked polymer film by photo-polymerization of the liquid monomers which were infused into the cross-linked polymer film. The formation of double-network structure significantly improved the electrical performance of the flexible devices. The charge mobility increased from 0.17 cm2V−1s−1 to 1.52 cm2V−1s−1 and on/off current ratio increased by one or two orders of magnitude. During the bending tests, the devices modified with double-network dielectric structure exhibited excellent mechanical stability even after hundreds of successive bending cycles along with different bending radius. For instance, the mobility of the devices modified with methyl methacrylate only reduced by 2% after 500 successive bending cycles with a bending radius of 10 mm. It is ascribed to the improvement of mechanical compatibility and decrease of adhesion energy between gate insulator and semiconductor with the double network dielectric structure. More importantly, this work is a unique example to demonstrate the importance of mechanical compatibility and adhesion energy between gate insulator and semiconductor on the mechanical stability of flexible OTFT. Furthermore, these results clearly demonstrated that this method is a promising tool to tune the semiconductor/dielectric interface, especially the mechanical compatibility and adhesion energy between semiconductor layer and dielectric layer, which has great potential for high performance flexible OTFTs with excellent mechanical stability.

Circular Structure for High Mechanical Bending Stability of a-IGZO TFTs

We employ a circular (Corbino) thin-film transistor (TFT) structure, in which the outer-ring is the drain and the inner-ring is the source, to improve the stability of amorphous–indium–gallium–zinc–oxide TFTs under tensile bending strain. We attribute the stability improvement to a more uniform electric field distribution across the circular channel, as it is isolated from local electric field crowding at sharp corners or channel edges. In addition, the effect of strain-induced increase in channel charge concentration is small in Corbino TFTs, owing to the larger outer-ring electrode, which depletes more electrons than the drain of rectangular TFTs. Furthermore, the circular shape results in bending direction independence, which is very important in multi-TFT circuits, where TFT orientation varies with position.