Strong Physical Unclonable Function Research Articles

Four-Dimensional Physical Unclonable Functions and Cryptographic Applications Based on Time-Varying Chaotic Phosphorescent Patterns.

Physical unclonable functions (PUFs) have attracted interest in demonstrating authentication and cryptographic processes for Internet of Things (IoT) devices. We demonstrated four-dimensional PUFs (4D PUFs) to realize time-varying chaotic phosphorescent randomness on MoS2 atomic seeds. By forming hybrid states involving more than one emitter with distinct lifetimes in 4D PUFs, irregular lifetime distribution throughout patterns functions as a time-varying disorder that is impossible to replicate. Moreover, we established a bit extraction process incorporating multiple 64 bit-stream challenges and experimentally obtained physical features of 4D PUFs, producing countless random 896 bit-stream responses. Furthermore, the weak and strong PUF models were conceptualized and demonstrated based on 4D PUFs, exhibiting superior cryptological performances, including randomness, uniqueness, degree of freedom, and independent bit ratio. Finally, the data encryption and decryption in pictures were performed by a single 4D PUF. Therefore, 4D PUFs could enhance the counterfeiting deterrent of existing optical PUFs and be used as an anticounterfeiting security strategy for advanced authentication and cryptographic processes of IoT devices.

A dependable and resource-frugal ring oscillator physically unclonable function

ABSTRACT Silicon Physical Unclonable Function (PUF) is a crucial component for hardware security, providing unique device identification in networks. PUF provides robust security for cryptographic keys and IC digital fingerprints. However, resource constraints in network devices limit its use in security protocols. To address this challenge, PUF offers a lightweight hardware security solution with two main types: strong PUF (e.g. arbiter PUF) and Ring Oscillator (RO) PUF. The first option produces large CRPs with improved security but incurs hardware overhead, whereas the second option offers lower overhead with smaller CRP size, leading to reduced security. This paper introduces a novel, cost-effective solution to enhance RO PUF security while reducing hardware limitations. Our proposal involves a resource sharing technique with scan flip-flops, multiplexers, and inverter logic. This approach takes advantage of existing scan chains in circuit netlists to reduce PUF area without sacrificing uniqueness. A specific set of test patterns and odd number of inverters transform the memory-based PUF into an RO PUF. Our solution also leverages pass transistor-based implementation to significantly reduce power consumption and area overhead. Simulation results show that our approach effectively reduces area and power consumption while maintaining PUF uniqueness.

PARLE-G: Provable Automated Representation and Analysis Framework for Learnability Evaluation of Generic PUF Compositions

Besides enormous research efforts in the design of Physically Unclonable Functions (PUFs), its vulnerabilities are still being exploited using machine learning (ML) based model-building attacks. Due to inherent complicacy in exploring and manually converging to a strong PUF composition, the challenge of building ML-attack resistant PUFs continues. Hence, it becomes imperative to develop an automated framework that can formally assess the learnability of different PUF constructions and compositions to guide the designer to explore resilient PUFs. In this work, we present an automated analysis framework (PARLE-G), to formally represent and evaluate the Probably Approximately Correct (PAC) learnability of PUF constructions and their compositions. A high-level specification language PUF-G has been developed to structurally represent any PUF composition comprising a specified set of primitive components and composition operations. The tool takes a PUF design represented in PUF-G language as input and returns its PAC learnability result, identifying a suitable PAC learning algorithm and the PAC model parameters based on the input PUF design. PUF designs proven to be learnable by PARLE-G are segregated into different classes based on the asymptotic complexity of their learnability bounds. Such automated analysis helps a designer to make informed design choices, thereby strengthening a PUF construction from the architectural level.

A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability.

Physical Unclonable Functions (PUFs) are significant in building lightweight Internet of Things (IoT) authentication protocols. However, PUFs are susceptible to attacks such as Machine-Learning(ML) modeling and statistical attacks. Researchers have conducted extensive research on the security of PUFs; however, existing PUFs do not always possess good statistical characteristics and few of them can achieve a balance between security and reliability. This article proposes a strong response-feedback PUF based on the Linear Feedback Shift Register (LFSR) and the Arbiter PUF (APUF). This structure not only resists existing ML modeling attacks but also exhibits good Strict Avalanche Criterion (SAC) and Generalized Strict Avalanche Criterion (GSAC). Additionally, we introduce a Two-Level Reliability Improvement (TLRI) method that achieves 95% reliability with less than 35% of the voting times and single-response generation cycles compared to the traditional pure majority voting method.

OTK-based PUF CRP obfuscation for IoT device authentication

The use of a strong physical unclonable function (PUF) for device authentication in resource-limited settings is promising but susceptible to machine learning (ML) attacks. Several defenses have been suggested, but they often have drawbacks such as increased hardware requirements, compromised reliability, and limited effectiveness against sophisticated ML attacks. To overcome these challenges, a one-time key-based (OTK) obfuscation approach has been proposed aiming to bolster the security of robust PUFs when facing machine learning-based attacks. The main concept involves obtaining multiple stable responses from the PUF and selecting one as the initial key for challenge obfuscation. However, only the challenge input for the selected key is stored on the device side. The server stores all the stable challenge-response pairs and uses this selected key for the first authentication only. After every authentication, the input to the key is updated on both sides. For response obfuscation random number generated by the server is used. Our proposed method can effectively prevent ML attacks with minimal hardware requirements. Arbiter-PUF and Rely-PUF as case studies are analyzed. Experimental findings indicate that when applied to 64 × 64 Arbiter and Rely PUF, our method significantly reduces the effectiveness of various machine learning attacks, resulting in a prediction accuracy of approximately 50.6% and 50.96% respectively. This level of accuracy is comparable to random guessing. The 64-bit OTK-PUF boasts an impressively compact storage footprint, comprising merely 164 Look-Up Tables (LUTs), 276 flip-flops, and a 512-bit of read-only memory (ROM). The execution of the protocol on the Vitis platform takes a mere 0.02 s on the device side.

A strong physical unclonable function with machine learning immunity for Internet of Things application

A strong physical unclonable function with machine learning immunity for Internet of Things application

A 3.02 pJ/Bit 3T-APS-Based In-Sensor Strong PUF Featuring Near-100% Hardware Reuse Ratio and High Resilience to Machine Learning Attacks

In this brief, we present an energy-efficient in-sensor strong physical unclonable function (PUF) based on the static entropy of 3-transistor active pixel sensor (3T-APS) structure that is widely-adopted in the CMOS image sensors (CIS). With ultra-small silicon area overhead of 0.25% dedicated to the added bias circuitries for column line and digital comparator for PUF bit generation, traditional 3T-APS-based CIS can be well-reused to construct the proposed strong PUF for authenticating the recorded images or videos. Taking advantage of the inherent high-resolution pixel array of CIS, the proposed strong PUF significantly extends the challenge-response-pair (CRP) space of the previous implementations. In addition, large CRP nonlinearity can be obtained by biasing the selected 3T-APS pixels at the subthreshold region, which further increases the complexity of the above extended CRP space and its resilience to various machine learning (ML) attacks. Moreover, the proposed strong PUF design is validated by the extensive measurement results of the prototype chips fabricated using a standard 65-nm CMOS process. Featuring a low energy consumption of 3.02 pJ/bit and a high area efficiency of 1.64×1033 bit/F2, prediction error of 49.1% 51.84% can be achieved under various ML attacks based on artificial neural network, logistic regression, support vector machine and covariance matrix adaptation evolution strategy, with the number of adopted CRPs for training up to 10 million.

Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead

Physical unclonable function (PUF) is a hardware security primitive with significant application potential. However, strong PUF is vulnerable to machine learning attacks based on modeling attacks. Although various resistance techniques have been proposed, strong PUF suffers from deficiencies in its resistance to machine learning attacks, hardware overhead, and reliability. This study proposes a highly reliable and secure lightweight PUF that complicates the original challenge using an internal response. Specifically, the internal response is used to determine the odd/even bit flip or left/right cyclic shift of the original challenge to achieve preliminary obfuscation, and byte substitution that exploits an S-box is performed on the preliminary obfuscated challenge to achieve deep nonlinear obfuscation. Experimental results on a Xilinx Artix-7 FPGA show that the proposed PUF is not only highly resistant to machine learning (ML) attacks but also has a low hardware overhead. An arbiter PUF(APUF), which uses the proposed obfuscated scheme with a 64-bit challenge length, was evaluated by three advanced machine learning algorithms with up to 600,000 challenge–response-pairs (CRPs) in the dataset, and the observed prediction accuracy was less than 56 %. Moreover, the PUF is unique, reliable, and has a significantly lower hardware overhead than other prior anti-attack PUFs.

CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack

Physical unclonable function (PUF) is a promising security-based primitive, which provides an extremely large number of responses for key generation and authentication applications. Various PUFs have been developed as central building blocks in cryptographic protocols and security architectures, however, the existing PUFs and their improvements are still vulnerable to modeling attacks (MA) with refined machine learning algorithms. In this article, a configurable butterfly delay chain-based PUF design framework is proposed to meet the requirements of randomness, reliability, uniqueness, and MA-resistance metrics. A configurable butterfly delay chain is introduced to create multiple pairs of symmetric paths and a strong PUF relying on the intrinsic delay fluctuations of two identical paths is built. Furthermore, a secure hash function is used to insert non-linearities into the PUF, and a BCH-based error correction algorithm is utilized to recover the actual responses under noisy environments. The proposed PUF is implemented on Xilinx FPGAs and three machine learning algorithms are used to evaluate the resistance against MA. Experimental results show that the randomness, reliability, and uniqueness of the proposed PUF are close to the ideal value (49.6%, 99.9%, and 49.9%, respectively), and the prediction accuracy reaches 50% that indicating a desirable resilient to MA.

MLMSA: Multilabel Multiside-Channel-Information Enabled Deep Learning Attacks on APUF Variants

To improve the modeling resilience of silicon strong physical unclonable functions (PUFs), in particular, the APUFs that yield a very large number of challenge response pairs (CRPs), a number of composited APUF variants such as XOR-APUF, interpose-PUF (iPUF), feed-forward APUF (FF-APUF), and OAX-APUF have been devised. When examining their security in terms of modeling resilience, utilizing multiple information sources such as power side channel information (SCI) or/and reliability SCI given a challenge is under-explored, which poses a challenge to their supposed modeling resilience in practice. Building upon multi-label/head deep learning model architecture, this work proposes Multi-Label Multi-Side-channel-information enabled deep learning Attacks (MLMSA) to thoroughly evaluate the modeling resilience of aforementioned APUF variants. Despite its simplicity, MLMSA can successfully break large-scaled APUF variants, which has not previously been achieved. More precisely, the MLMSA breaks 128-stage 30-XOR-APUF, (9,9)-and (2,18)-iPUFs, and (2,2,30)-OAX-APUF when CRPs, power SCI and reliability SCI are concurrently used. It breaks 128-stage 12-XOR-APUF and (2,2,9)-OAX-APUF even when only the easy-to-obtain reliability SCI and CRPs are exploited. The 128-stage six-loop FF-APUF and one-loop 20-XOR-FF-APUF can be broken by simultaneously using reliability SCI and CRPs. All these attacks are normally completed within an hour with a standard personal computer. Therefore, MLMSA is a useful technique for evaluating other existing or any emerging strong PUF designs.

Dynamic self-test scheme and authentication protocol for improving robustness of strong PUF

In the realm of IoT applications, where resources are limited, physical unclonable functions (PUFs) have emerged as a promising encryption strategy due to their lightweight and high-security. While several PUFs have been proposed, there is still a need to balance low-cost and high security given the constraints of hardware resources. This paper presents a PUF design based on sub-threshold current arrays that offers high resource utilization. To improve the robustness of PUF response, a dynamic control and self-test scheme is proposed. Additionally, a high-efficiency authentication protocol is developed to enhance the utilization of CRPs. Even if an unstable response is generated, the proposed protocol considers it to be authenticated successfully as long as the degree of stability of the response is within a specific range. The PUF circuit occupies only 377.4 nm2 and achieves good uniqueness and stability with a bit error rate (BER) of 0.45% per 10 °C over a temperature range of −40 °C to 80 °C.

A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF.

An SSL-PUF Based Access Authentication and Key Distribution Scheme for the Space-Air-Ground Integrated Network.

The Space-Air-Ground Integrated Network (SAGIN) expands cyberspace greatly. Dynamic network architecture, complex communication links, limited resources, and diverse environments make SAGIN's authentication and key distribution much more difficult. Public key cryptography is a better choice for terminals to access SAGIN dynamically, but it is time-consuming. The semiconductor superlattice (SSL) is a strong Physical Unclonable Function (PUF) to be the hardware root of security, and the matched SSL pairs can achieve full entropy key distribution through an insecure public channel. Thus, an access authentication and key distribution scheme is proposed. The inherent security of SSL makes the authentication and key distribution spontaneously achieved without a key management burden and solves the assumption that excellent performance is based on pre-shared symmetric keys. The proposed scheme achieves the intended authentication, confidentiality, integrity, and forward security, which can defend against masquerade attacks, replay attacks, and man-in-the-middle attacks. The formal security analysis substantiates the security goal. The performance evaluation results confirm that the proposed protocols have an obvious advantage over the elliptic curve or bilinear pairings-based protocols. Compared with the protocols based on the pre-distributed symmetric key, our scheme shows unconditional security and dynamic key management with the same level performance.

A PUF-Based Key Storage Scheme Using Fuzzy Vault

Physical Unclonable Functions (PUFs) are considered attractive low-cost security anchors in the key generation scheme. The helper data algorithm is usually used to transform the fuzzy responses extracted from PUF into a reproducible key. The generated key can be used to encrypt secret data in traditional security schemes. In contrast, this work shows that the fuzzy responses of both weak and strong PUFs can be used to secretly store the important data (e.g., the distributed keys) directly by an error-tolerant algorithm, Fuzzy Vault, without the traditional encryption algorithm and helper data scheme. The locking and unlocking methods of our proposal are designed to leverage the feature of weak and strong PUFs relatively. For the strong PUFs, our proposal is a new train of thought about how to leverage the advantage of strong PUFs (exponential number of challenge-response pairs) when used in the field. The evaluation was performed on existing weak PUF and strong PUF designs. The unlocking rate and runtime are tested under different parameters and environments. The test results demonstrate that our proposal can reach a 100% unlocking rate by parameter adjustment with less than 1 second of locking time and a few seconds of unlocking time. Finally, the tradeoff between security, reliability, and overhead of the new proposal is discussed.

Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA

Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge- Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.

A Provably Secure Strong PUF Based on LWE: Construction and Implementation

We construct a strong physical unclonable function (PUF) with provable security against machine learning (ML) attacks on both classical and quantum computers. The security is guaranteed by the cryptographic hardness of learning decryption functions of public-key cryptosystems, and the hardness of the learning-with-errors (LWE) problem defined on integer lattices. We call our construction the lattice PUF. We construct lattice PUF with a physically obfuscated key and an LWE decryption function block. To allow deployments in different scenarios, we demonstrate designs with different latency-area trade-offs. A compact design uses a highly serialized linear-feedback shift register (LFSR) and LWE decryption function, while a latency-optimized design uses an unrolled LFSR and a parallel datapath. We prototype lattice PUF designs with <inline-formula><tex-math notation="LaTeX">$2^{136}$</tex-math></inline-formula> challenge-response pairs (CRPs) on a spartan 6 field-programmable gate array (FPGA). In addition to theoretical security guarantee, we evaluate empirical resistance to the various leading ML techniques: the prediction error remains above <inline-formula><tex-math notation="LaTeX">$49.76\%$</tex-math></inline-formula> after 1 million training CRPs. The resource-efficient design requires only 45 slices for PUF logic proper, and 27 slices for reverse fuzzy extractor. The latency-optimized design achieves a <inline-formula><tex-math notation="LaTeX">$148X$</tex-math></inline-formula> reduction in latency, at a <inline-formula><tex-math notation="LaTeX">$10X$</tex-math></inline-formula> increase in PUF hardware utilization. The mean uniformity of PUF responses is <inline-formula><tex-math notation="LaTeX">$49.98\%$</tex-math></inline-formula> , the mean uniqueness is <inline-formula><tex-math notation="LaTeX">$50.00\%$</tex-math></inline-formula> , and the mean reliability is <inline-formula><tex-math notation="LaTeX">$1.26\%$</tex-math></inline-formula> .

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries, such as logistics and freight transportation. To further promote RFID tags adoption, security, power consumption, and cost have always been issues of general concern. This article presents the first synergy of the RFID tag with embedded resistive RAM (RRAM) array and RRAM-based reconfigurable strong physical unclonable function (R-SPUF). The RRAM not only meets the mass storage and technology downscaling but also renders the ultralow-cost “1-cent RFID tag” more feasible. Moreover, the R-SPUF facilitates multiple initializations until a satisfactory distribution and has strong secure keys benefiting from its reconfigurability that improves both safety and reliability. The complete system operates at 13.56 MHz and is compliant with the ISO14443-A and ISO10373-6 (test) protocols. The RFID tag was fabricated on a 1.1-mm2 die based on the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. Without resorting to the charge pumps for RRAM read–write operations, the total power consumption is as low as 52.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , of which the RRAM dissipates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.2~\mu \text{W}$ </tex-math></inline-formula> under a wireless power supply.

Cryptanalysis of Strong Physically Unclonable Functions

Physically unclonable functions (PUFs) are being proposed as a low-cost alternative to permanently store secret keys or provide device authentication without requiring nonvolatile memory, large e-fuses, or other dedicated processing steps. In the literature, PUFs are split into two main categories. The so-called strong PUFs are mainly used for authentication purposes; hence, also called authentication PUFs. They promise to be lightweight by avoiding extensive digital post-processing and cryptography. The so-called weak PUFs, also called key generation PUFs, can only provide authentication when combined with a cryptographic authentication protocol. Over the years, multiple research results have demonstrated that Strong PUFs can be modeled and attacked by machine learning (ML) techniques. Hence, the general assumption is that the security of a strong PUF is solely dependent on its security against ML attacks. The goal of this article is to debunk this myth, by analyzing and breaking three recently published Strong PUFs (Suresh et al., VLSI Circuits 2020; Liu et al., ISSCC 2021; and Jeloka et al., VLSI Circuits 2017). The attacks presented in this article have practical complexities and use generic symmetric key cryptanalysis techniques.

Enhancing Strong PUF Security With Nonmonotonic Response Quantization

Strong physical unclonable functions (PUFs) provide a low-cost authentication primitive for resource-constrained devices. However, most strong PUF architectures can be modeled through learning algorithms with a limited number of CRPs. In this article, we introduce the concept of nonmonotonic response quantization for strong PUFs. Responses depend not only on which path is faster but also on the distance between the arriving signals. Our experiments show that the resulting PUF has increased security against learning attacks. To demonstrate, we designed and implemented a nonmonotonically quantized ring oscillator-based PUF in 65-nm technology. Measurement results show nearly ideal uniformity and uniqueness with a bit error rate of 13.4% over the temperature range from 0 °C to 50 °C.

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

The advanced integrated circuits have been widely used in various situations including the Internet of Things, wireless communication, etc. But its manufacturing process exists unreliability, so cryptographic chips must be rigorously tested. Due to scan testing provides high test coverage, it is applied to the testing of cryptographic integrated circuits. However, while providing good controllability and observability, it also provides attackers with a backdoor to steal keys. In the text, a novel protection scheme is put forward to resist scan-based attacks, in which we first use the responses generated by a strong physical unclonable function circuit to solidify fuse-antifuse structures in a non-linear shift register (NLSR), then determine the scan input code according to the configuration of the fuse-antifuse structures and the styles of connection between the NLSR cells and the scan cells. If the key is right, the chip can be tested normally; otherwise, the data in the scan chain cannot be propagated normally, it is also impossible for illegal users to derive the desired scan data. The proposed technique not only enhances the security of cryptographic chips, but also incurs acceptable overhead.