Strong Inversion Regime Research Articles

Impact of quantum effects on the short channel effects of III–V nMOSFETs in weak and strong inversion regimes

This paper investigates the impact of quantum effects on the increase of short channel effects in III–V MOSFETs. First of all, contrary to the results obtained by other groups [1,2], quantum confinement has been found to play no role on the short channel effects occurring in the subthreshold regime. In this regime, the main origin of the increase of SCEs is simply due to the higher dielectric constant of III–V semiconductors. However, in strong inversion regime, the increase of the electrical equivalent oxide thickness due to quantum confinement is shown to have a detrimental impact on the drain induced barrier lowering. These results further confirm that III–V technologies will require innovative devices like ultra-thin films or multi-gate structures to ensure a better control short channel effects.

Temperature dependent compact modeling of gate tunneling leakage current in double gate MOSFETs

The temperature dependence of the gate leakage current has been developed for Double Gate (DG) MOSFETs. This model is compared with experimental data measured in Trigate MOSFETs at various temperatures with SiON as a dielectric material and SiO2 as an interfacial layer. The gate leakage current measurements at different temperatures show two different transport mechanisms, direct tunneling (DT) gate leakage and Trap-Assisted-Tunneling (TAT) current. Our analysis based on leakage current measurements in the above threshold regime for different temperatures shows that the DT current is clearly dominant over the TAT, while the opposite happens below threshold. Our model is able to explain the gate tunneling current in terms of gate voltage for different temperatures. The results of the DT current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements.

Effect of bias conditions on pressure sensors based on AlGaN/GaN High Electron Mobility Transistor

This work reports the bias and pressure sensitivity of AlGaN/GaN High Electron Mobility Transistors (HEMTs) sensing elements strategically placed on a pressure sensitive diaphragm clamped at its edges. The sensitivity was over 150 times greater in the weak inversion regime than in the strong inversion regime of the HEMT, leading to a drain current change of >38% when a pressure of 50bar was applied. The sensitivity of the HEMT to pressure followed an exponential dependence from atmospheric pressure up to 80bar, behaviour explained by the response of the density of a two-dimensional electron gas to pressure induced changes in the HEMT threshold voltage in the weak inversion regime. Finally, it was found that the sensitivity of the HEMT was maximum when it was situated in the middle of the diaphragm, whereas a device mounted over the clamping point showed less than 0.02% change in drain current when pressure change of 50bar was applied.

Noise spectroscopy as an equilibrium analysis tool for highly sensitive electrical biosensing

We demonstrate an approach for highly sensitive bio-detection based on silicon nanowire field-effect transistors by employing low frequency noise spectroscopy analysis. The inverse of noise amplitude of the device exhibits an enhanced gate coupling effect in strong inversion regime when measured in buffer solution than that in air. The approach was further validated by the detection of cardiac troponin I of 0.23 ng/ml in fetal bovine serum, in which 2 orders of change in noise amplitude was characterized. The selectivity of the proposed approach was also assessed by the addition of 10 μg/ml bovine serum albumin solution.

MOSFET Drain Current Noise Modeling With Effective Gate Overdrive and Junction Noise

In this letter, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source-bulk junction and the drain-bulk junction is presented. A unified analytical expression is derived to ensure excellent continuity with smooth transition of drain current noise from weak- to strong-inversion regimes, including the moderate-inversion region. Excellent agreement between simulated and extracted noise data has shown that the proposed model is accurate over different dimensions and operating conditions.

Temperature Dependence of Inversion Layer Carrier Concentration and Hall Mobility in 4H-SiC MOSFETs

Hall measurements on NO annealed 4H-SiC MOS gated Hall bars are reported in the temperature range 77 K- 423 K. The results indicate higher carrier concentration and lower trapping at increased temperatures, with a clear strong inversion regime at all temperatures. In stark contrast to Si, the Hall mobility increases with temperature for 77 K-373K, above which the mobility decreases slightly. The maximum experimental mobility was found to be ~50 cm2 V-1 s-1 which is only about 10% of the 4H-SiC bulk mobility indicating that while NO annealing drastically improves trapping, it does not improve the mobility significantly. Supporting modeling results strongly suggest the presence of a disordered SiC channel region.

Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation

Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piecewise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate, and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and we verify its performance using measured results.

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)

Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.

Behavior of Low-Frequency Noise in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors for Different Impurity Concentrations

In this study, we investigated the behavior of the low-frequency noise of n-channel metal–oxide–semiconductor field-effect transistors as a function of gate overdrive from the viewpoints of subthreshold slope and normalized transconductance. We prepared devices with different uniformities of channel impurity, carrier mobility, and the degree of the short-channel effect by halo implantation and changing the substrate impurity concentration and gate length. It was found that the small subthreshold swing value increases the slope of noise intensity in the subthreshold regime, probably resulting from random nature of the diffusion transport. On the other hand, the magnitude of noise intensity in the strong inversion regime is related to the normalized transconductance, where a small number of scattering events in the channel realize low noise intensity.

Modeling local electrical fluctuations in 45 nm heavily pocket-implanted bulk MOSFET

Modeling local electrical fluctuations on pocket transistor is a challenging task, especially for relatively long gate transistors. Previous work highlighted and qualitatively explain the anomalously high random dopant induced increase of local fluctuations in rather long and heavily pocket device but could not accurately provide the amplitude of the phenomenon. In this paper, a new physical mismatch model is introduced. It is based on the three-transistor model, where one transistor is used to model the channel region and the other two for the pocket regions. This mismatch model provides both qualitative and quantitative mismatch results for all transistor gate lengths and furthermore, it is valid from weak to strong inversion regimes. After the model presentation, a detailed discussion of the qualitative results is performed. Afterwards, the experimental setup is presented. Finally, the physical parameters of the model are characterized and then the resulting level of fluctuations is shown to well model the experimental results.

A generic numerical model for detection of terahertz radiation in MOS field-effect transistors

Abstract A generic numerical model which is valid both in the strong inversion regime and sub-threshold regime for the detection of terahertz radiation utilizing Metal–Oxide–Semiconductor (MOS) Field-Effect Transistors (FETs) is developed in this paper. A general carrier density equation and gate leakage current are coupled to the basic hydrodynamic equations which govern the electron transport in the 2D channel of the MOS field-effect transistor to obtain the numerical solution; a progress-based photo-response signal of the terahertz radiation of MOSFET is calculated. The simulation results are compared with existing analytical results, proving the validity of the proposed numerical model and overcoming limitations of the analytical theories.

A model of electrical conduction across the grain boundaries in polycrystalline-silicon thin film transistors and metal oxide semiconductor field effect transistors

An electrical conduction model of carrier transport across the grain boundaries (GBs) in polycrystalline silicon (PX-Si) films is developed by considering four conduction mechanisms, a Gaussian energy distribution for GB interface states and the GB scattering effects. The model is applicable over a wide range of temperature and grain size. It is found that the GB scattering potential and the GB distribution parameter are function of temperature but are independent of doping density and grain size. The conduction model is able to explain the dependence of transfer and output characteristics of thin film transistors (TFTs) on the temperature and grain size in the strong inversion regime. The variation of effective mobility and drain current for n-channel TFTs and metal oxide semiconductor field effect transistors with gate bias voltage and grain sizes is also studied. A satisfactory agreement is obtained between the theoretical investigations and the available experimental data.

Influence of Band Non-Parabolicity on Few Ballistic Properties of III–V Quantum Wire Field Effect Transistors Under Strong Inversion

A simplified yet analytical approach on few ballistic properties of III-V quantum wire transistor has been presented by considering the band non-parabolicity of the electrons in accordance with Kane's energy band model using the Bohr-Sommerfeld's technique. The confinement of the electrons in the vertical and lateral directions are modeled by an infinite triangular and square well potentials respectively, giving rise to a two dimensional electron confinement. It has been shown that the quantum gate capacitance, the drain currents and the channel conductance in such systems are oscillatory functions of the applied gate and drain voltages at the strong inversion regime. The formation of subbands due to the electrical and structural quantization leads to the discreetness in the characteristics of such 1D ballistic transistors. A comparison has also been sought out between the self-consistent solution of the Poisson's-Schrodinger's equations using numerical techniques and analytical results using Bohr-Sommerfeld's method. The results as derived in this paper for all the energy band models gets simplified to the well known results under certain limiting conditions which forms the mathematical compatibility of our generalized theoretical formalism.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ldquocrossover pointrdquo). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Non-Gaussianity of noise in n-type metal oxide semiconductor field effect transistor

On the basis of the number fluctuation model of n-type metal oxide semiconductor field effect transistor （nMOSFET），non-Gaussianity of noise in nMOSFET was studied by the quadratic sum of the bicoherence，which belongs to higher order statistics. Comparing nMOSFETs test noise with Monte Carlo simulative noise，we proved that there is non-Gaussianity in nMOSFTs noise, that the noises non-Gaussian degree in small size devices is stronger than that in large size devices, and that the non-Gaussian degree of nMOSFTs noise in strong inversion and linear regime increase with the drain-source voltage. The physical mechanism of nMOSFET noise is discussed from Monte Carlo simulation and the central limit theorem.

Modeling and Analysis of Body Potential of Cylindrical Gate-All-Around Nanowire Transistor

A new physically based classical model for the potential distribution of an undoped body cylindrical gate-all-around nanowire transistor is proposed. The model is based on the analytical solution of 2-D Poisson's equation in a cylindrical coordinate system and is valid for both (1) weak and strong inversion regimes, (2) long and short-channel transistors, and (3) body surfaces and centers. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body radii pass through a single common point (termed a ldquocrossover pointrdquo). It is found that, at this crossover point, there is no potential drop (ldquopseudo flatband conditionrdquo) along the radial direction. Using the concept of crossover point, the effect of body radius on the threshold voltage of undoped body multigate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects, the effective subthreshold slope factor is mainly dictated by the potential at the body center rather than that at the surface. All the models are validated against a professional numerical device simulator.

Design of chaotic analog noise generators with logistic map and MOS QT circuits

In this paper a method to design chaotic analog noise generators using MOS transistors is presented. Two aspects are considered, the determination of operation regime of the MOS circuit and the statistical distribution of its output signal. The operation regime is related with the transconductance linear (TL: translinear) principle. For MOS transistors this principle was originally formulated in weak inversion regime; but, strong inversion regimen is used because in 1991, Seevinck and Wiegerink made the generalization for this principle. The statistical distribution of the output signal on the circuit, which should be a uniform distribution, is related with the parameter value that rules the transfer function of the circuit, the initial condition (seed) in the circuit and its operation as chaotic generator. To show these concepts, the MOS Quadratic Translinear circuit proposed by Wiegerink in 1993 was selected and it is related with the logistic map and its properties. This circuit will operate as noise generator if it works in strong inversion regime using current-mode approach when the parameter that rules the transfer function is higher than the onset chaos value (3.5699456…) for the logistic map.

Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs

Models for short-channel DG and GAA MOSFETs are presented. In the subthreshold regime, the electrostatics of the device is dominated by the capacitive coupling between the electrodes, which is analyzed by conformal mapping techniques. In the strong inversion regime, the device behavior is dominated by the inversion charge, allowing a 1D analysis. The models are verified by comparison with numerical device simulations. The electrostatic properties of the DG and GAA are compared, demonstrating the superior short-channel behavior of the GAA design.

Three-Dimensional Simulation of One-Dimensional Transport in Silicon Nanowire Transistors

We present a simulation study of silicon nanowire transistors, based on an in-house code providing the self-consistent solution of Poisson, Schrodinger, and continuity equations on a generic three-dimensional domain. The main assumption, based on the very small nanowire cross section considered, is that an adiabatic approximation can be applied to the Schrodinger equation, so that transport occurs along one-dimensional sub- bands. Different subband transport models are considered, such as ballistic transport, either including quantum tunneling or not, and drift-diffusion. We show that nanowire transistors exhibit good control of short channel effects, and that barrier tunneling is significant in the strong inversion regime even for longer devices, while it is significant in subthreshold only for the shortest channel lengths. Finally, we show that a subband-based transport model allows to reach a very good trade off between physical accuracy of the simulation and computing time.

Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks

Capacitance-voltage (CV) measurements on germanium metal oxide semiconductor (MOS) structures show unusual frequency behavior compared to their silicon counterparts—a low-frequency behavior of the high-frequency CV characteristics is observed in the inversion regime, and the experimental CV curves in the depletion regime exhibit large features that have been attributed to high densities of interface defects (Dit). In this paper, an electrical model is proposed to give insights on the fundamental mechanisms impacting Ge structures from a careful analysis of these CV measurements. Thanks to this analytical model, both CV and GV (conductance-voltage) characteristics have been accurately simulated over a large range of gate voltages and frequencies. The modeling of the strong inversion regime confirms that the generation-recombination of minority carriers is assisted by bulk traps and shows that a small level of impurities in Ge—in the 1015–1016percm3 range—can explain the frequency dispersion observed in the CV curves. The modeling in the depletion regime takes into account the fast minority carrier response in Ge. This clearly shows that the filling of the interface traps by minority carriers is essential for explaining the large features observed in the weak inversion regime and consequently that common Dit extraction techniques used on Si cannot be applied any longer to Ge MOS structures.