Strong Error Correction Capability Research Articles

On Ordinary Words of Standard Reed–Solomon Codes over Finite Fields

Reed–Solomon codes are widely used to establish a reliable channel to transmit information in digital communication which has a strong error correction capability and a variety of efficient decoding algorithm. Usually we use the maximum likelihood decoding (MLD) algorithm in the decoding process of Reed–Solomon codes. MLD algorithm relies on determining the error distance of received word. Dür, Guruswami, Wan, Li, Hong, Wu, Yue and Zhu et al. got some results on the error distance. For the Reed–Solomon code [Formula: see text], the received word [Formula: see text] is called an ordinary word of [Formula: see text] if the error distance [Formula: see text] with [Formula: see text] being the Lagrange interpolation polynomial of [Formula: see text]. We introduce a new method of studying the ordinary words. In fact, we make use of the result obtained by Y.C. Xu and S.F. Hong on the decomposition of certain polynomials over the finite field to determine all the ordinary words of the standard Reed–Solomon codes over the finite field of [Formula: see text] elements. This completely answers an open problem raised by Li and Wan in [On the subset sum problem over finite fields, Finite Fields Appl. 14 (2008) 911–929].

Blind Recognition of Parameters of Reed Solomon Code from Intercepted Erroneous Codewords

Error correcting codes are designed for reliable transmission of digital information over a noisy channel. Several papers have been published on blind identification of binary FEC codes but papers reported on the identification of non-binary error correcting codes are less. Due to its strong error correction capability, RS (Reed-Solomon) code is being used widely. So technique for blind recognition of RS code is required to analyse intercepted signal as well as for intelligent communication. This paper presents a technique for extraction of parameters of Reed-Solomon code from intercepted demodulated bitstream. The proposed algorithm is very simple and hence it is very practical for hardware implementation. Our approach has been verified using MATLAB simulation.

Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices

Flash memory has been developed with bit density improvement, technology scaling, and 3-D stacking. With this trend, its reliability has been significantly degraded. Error correction code (ECC), such as low-density parity code (LDPC), which has strong error correction capability, has been deployed to solve this problem. However, one of the critical issues of LDPC is that it would introduce a long decoding latency on devices with low reliability. In this case, tail latency would happen, which will significantly impact the quality of service. In this work, a set of smart refresh schemes is proposed to optimize the tail latency. The basic idea of the work is to refresh data when the accessed data have a long decoding latency. Two smart refresh schemes are proposed for this work. The first refresh scheme is designed to refresh data with a long access latency when they are accessed several times. The second refresh scheme is designed to periodically check data with an extremely long access latency and refresh them. To further optimize the refresh overhead caused by the above refresh schemes, a dual-ECC-based refresh scheme is proposed. Besides, a mathematical model for all proposed schemes is constructed to clarify the benefit of each scheme. The experimental results show that the proposed schemes can significantly improve the tail latency with acceptable overhead. What is more, the access performance is well maintained compared with the state-of-the-art work.

Minimum Distance Optimization with Chord Edge Growth for High Girth Non-Binary LDPC Codes

Short or moderate-length non-binary low-density parity-check (NB-LDPC) codes have the potential applications in future low latency and high-reliability communication thanks to the strong error correction capability and parallel decoding. Because of the existence of the error floor, the NB-LDPC codes usually cannot satisfy very low bit error rate (BER) requirements. In this paper, a low-complexity method is proposed for optimizing the minimum distance of the NB-LDPC code in a progressive chord edge growth manner. Specifically, each chord edge connecting two non-adjacent vertices is added to the Hamiltonian cycle one-by-one. For each newly added chord edge, the configuration of non-zero entries corresponding to the chord edge is determined according to the so-called full rank condition (FRC) of all cycles that are related to the chord edge in the obtained subgraph. With minor modifications to the designed method, it can be used to construct the NB-LDPC codes with an efficient encoding structure. The analysis results show that the method for designing NB-LDPC codes while using progressive chord edge growth has lower complexity than traditional methods. The simulation results show that the proposed method can effectively improve the performance of the NB-LDPC code in the high signal-to-noise ratio (SNR) region. While using the proposed scheme, an NB-LDPC code with a quite low BER can be constructed with extremely low complexity.

Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory

By stacking layers vertically, the adoption of 3D NAND has significantly increased the capacity for storage systems. The complex structure of 3D NAND introduces more errors than planer flash. To address the reliability issue, low-density parity-check (LDPC) code with a strong error correction capability is now widely applied on 3D NAND flash memory. However, LDPC has long decoding latency when the raw bit error rates (RBER) are high. This is because it needs fine-grained soft sensing between voltage states to iteratively decode the raw data. Multiple sensing voltages are applied on flash cell array to gain necessary information for decoding. In this article, a new sensing level placement scheme with reduced number of sensing levels is proposed. The basic idea for the placement scheme is motivated by three asymmetric error characteristics of flash memory: the asymmetric errors between different states, the asymmetric errors caused by voltage left-shifts and right-shifts and asymmetric errors among layers in a 3D NAND flash block. With awareness of these three types of error characteristics, reduced number of sensing levels are placed to achieve reduced read latency for LDPC decoding while maintaining the error correction capability of LDPC. Experiment analysis shows that the proposed scheme achieves significant performance improvement.

Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash

3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly adopting LDPC codes induces high decoding latency due to iterative updating of log-likelihood ratio (LLR) information in the decoding process. Increasing LLR information accuracy can greatly improve decoding performance. In this paper, we propose EMAL: using error modes aware LDPC codes for further enhancing the decoding performance of 3-D TLC NAND flash. We first obtain 3-D TLC error modes based on an FPGA testing platform, and then exploit the error modes to optimize LLR information and enable the decoding to converge at a high speed. The simulation results show that the decoding performance is significantly improved, resulting in reduced bit error rates and decoding latency.

Some results on ordinary words of standard Reed-Solomon codes

The Reed-Solomon codes are widely used to establish a reliable channel to transmit information in digital communication which has a strong error correction capability and a variety of efficient decoding algorithm. We usually use the maximum likelihood decoding algorithm (MLD) in the decoding process of Reed-Solomon codes. MLD algorithm lies in determining its error distance. Li, Wan, Hong and Wu et al obtained some results on the error distance. For the Reed-Solomon code $RS_q({\mathbb F}_q^*, k)$, the received word ${\bf u}$ is called an ordinary word of $RS_q({\mathbb F}_q^*, k)$ if the error distance $d({\bf u}, RS_q({\mathbb F}_q^*, k)) = n-\deg(u(x))$ with $u(x)$ being the Lagrange interpolation polynomial of ${\bf u}$. In this paper, we make use of the polynomial method and particularly, we use the KŚnig-Rados theorem on the number of nonzero solutions of polynomial equation over finite fields to show that if $q\geq 4, 2\leq{k}\leq{q-2}$, then the received word ${\bf u}\in{\mathbb F}_q^{q-1}$ of degree $q-2$ is an ordinary word of $RS_q({\mathbb F}_q^*, k)$ if and only if its Lagrange interpolation polynomial $u(x)$ is of the form $ u(x) = \lambda\sum\limits_{i = k}^{q-2}a^{q-2-i}x^i+f_{\leq k-1}(x) $ with $a, \lambda\in{\mathbb F}_q^*$ and $ f_{\leq k-1}(x)\in {\mathbb F}_q[x]$ being of degree at most $k-1$. This answers partially an open problem proposed by J.Y. Li and D.Q. Wan in [On the subset sum problem over finite fields, Finite Fields Appls. 14 (2008), 911-929].

ILDPC coded RCM scheme with optimised interleaver

In this study, an irregular low-density parity-check (iLDPC) coded rate compatible modulation (iLDPC-RCM) is proposed. A particularly designed interleaver is inserted between LDPC and RCM such that a fast convergence and a low bit-error rate (BER) can be achieved. The combination of strong error correction capability of irregular LDPC code and the seamless adaptation of RCM enables the proposed scheme to achieve a robust and spectrally efficient transmission over time-varying channels. In addition, a joint belief propagation algorithm is proposed to lower the BER of iLDPC-RCM and speed up the convergence of iterative decoding. Simulation results show that the proposed iLDPC-RCM improves the BER and throughput performance while maintaining an acceptable computational complexity at the same time, validating its advantages over the regular LDPC coded RCM with the same coding rate.

Design and Analysis of Non-Binary LDPC-CPM System for Hybrid Check Matrix Construction Algorithm of WSN.

In order to enhance the reliability and anti-interference performance of wireless sensor network (WSN) data transmission, this paper designs the low power scheme of the WSN from the angle of error correction coding and proposes the hybrid check matrix construction (HC) algorithm based on iterative coding algorithms with linear coding complexity. The algorithm first improves the traditional iterative coding algorithm, making it suitable for non-binary low-density parity check (LDPC) codes. Then, the algorithm applies the backward iteration method to change the coding scheme and uses the check matrix construction method so that the progressive edge growth (PEG) algorithm has a lower triangular structure, which is used as a base matrix. An improved quasi-cyclic LDPC (QC-LDPC) algorithm, with a lower triangular structure, is used to generate a cyclic shift matrix and a finite domain coefficient matrix. Simultaneously, the short loop is eliminated and the optimal check matrix is selected for use in the channel coding process. The non-binary LDPC-CPM system is modeled and simulated. The simulation results show that the non-binary LDPC code constructed by the HC algorithm not only has linear coding and storage complexity but also has strong error correction capability. The design of non-binary LDPC-CPM system parameters can enhance the reliability, anti-jamming capability and reduce the complexity and reduce the complexity of the WSN.

A QR code based tracing method for fresh pork quality in cold chain

AbstractFresh pork is a meat that many people choose to eat in daily lives, and it is becoming more important to devise a method for ensuring the quality and safety of fresh pork. Combined with the meat quality of the cold chain and the environmental information collection program, this study presents a QR code based tracing method for a quality tracing system. This method includes a correction recognition test for the final design of the QR code. The results show that QR code can store large amounts of traceability information, with strong error correction capability, and can provide a great advantage in scanning recognition. In the process of consumption, consumers can easily obtain fresh pork quality information by scanning the QR code with a mobile phone, rather than having to choose a piece of meat to purchase based only on a visual observation of the meat.Practical applicationsIn this study, the design of the temperature acquisition scheme was verified in SMEs (small and medium enterprises), the results show that the data transmission is stable. The generated QR codes were tested in some supermarkets, have strong error correction capability, and can meet the retroactive requirements. According to this research, when the damage to the traceability barcode is beyond the range of 30% before the barcode enters circulation, the barcode needs to be reprinted.

RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory

3D-multi-level cell (MLC) NAND flash memory adopts 3D stack technology and stores two bits per cell, leading to improved storage capacities, but sacrificing data reliability. Low-density parity-check (LDPC) codes showing strong error correction capability benefit from their soft decision decoding, which is widely exploited to guarantee data reliability. Nevertheless, adopting LDPC codes can introduce a concern about read performance, because their iterative soft-decision decoding requires Log-Likelihood Ratio (LLR) information, called soft decision information, by applying multi-sensing voltages. This process of obtaining LLR information leads to high sensing and transferring latencies, lowering down 3D-MLC read performance. In particular, when raw bit error rates (RBER) are much higher due to the long retention periods and program/erase (P/E) cycles, this problem becomes more serious. In this paper, we propose a RBER-aware multi-sensing scheme for reducing sensing and transferring latencies, and thus improving read performance. This proposed scheme exploits the variations of RBER in flash pages with the increase of retention time and P/E cycles to dynamically apply sensing voltages. Simulation results show that this scheme significantly decreases the number of required sensing voltages while maintaining LDPC error correction capability, enhancing 3D-MLC read performance.

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance

By scaling down to smaller cell size, NAND flash has significantly increased the storage capacity in order to lower the unit cost down. However, the reliability is sacrificed due to much higher raw bit error rates. As a result, conventional error correction codes (ECCs), such as BCH codes, are not sufficient. Low-density parity check (LDPC) codes with stronger error correction capability are adopted in NAND flash to guarantee data reliability. However, read performance using LDPC is poor because of its decoding complexity. It has been found that flash cells with fewer electrons are more prone to program interference errors. As a result, program interference errors show the characteristic of value dependence. This characteristic can be exploited and translated into extra information facilitating the decoding convergence. Motivated by this observation, we propose PEAL: a flash <underline>p</underline>rogram interference <underline>e</underline>rror <underline>a</underline>ware <underline>L</underline>DPC scheme to enhance the decoding performance. PEAL integrates the obtained extra information from the value dependence into the soft-to-hard decision process in LDPC decoding to decrease decoding iterations and improve the decoding convergence speed. Simulation results show that decoding iterations are reduced by up to 69.37% and the decoding convergence speed is improved by up to 2.5×, compared with the normalized min-sum (NMS) algorithm with 2KB information lengths at an approximate raw bit error rate of 11.5 × 10 −3 .

Study on the Decoder for Reed-Solomon (255, 239) Code

Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

Reducing latency overhead caused by using LDPC codes in NAND flash memory

Semiconductor technology scaling makes NAND flash memory subject to continuous raw storage reliability degradation, leading to the demand for more and more powerful error correction codes. This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as low-density parity-check (LDPC) codes become very natural alternative options. However, fine-grained soft-decision memory sensing must be used in order to fully leverage the strong error correction capability of LDPC codes, which results in significant data access latency overhead. This article presents a simple design technique that can reduce such latency overhead. The key is to cohesively exploit the NAND flash memory wear-out dynamics and impact of LDPC code structure on decoding performance. Based upon detailed memory device modeling and ASIC design, we carried out simulations to demonstrate the potential effectiveness of this design method and evaluate the involved trade-offs.

Multivalued associative memories based on recurrent networks

A multivalued neural associative memory model based on a recurrent network structure is proposed. This model adopts the same principle proposed in the authors' previous work, the exponential correlation associative memories (ECAM). The model also has a very high storage capacity and strong error-correction capability. The major components of the new model include a weighted average process and some similarity-measure computation. As in ECAM, in order to enhance the differences among the weights and make the largest weights more overwhelming, the new model incorporates a nonlinear function in the calculation of weights. Several possible similarity measures suitable for this model are suggested. Simulation results of the performance of the new model with different measures show that, loaded with 500 64-component patterns, the model can sustain noise with power about one fifth to three fifths of the average signal power.

On the Characteristics of the Autoassociative Memory with Nonzero-Diagonal Terms in the Memory Matrix.

A statistical method is applied to explore the unique characteristics of a certain class of neural network autoassociative memory with N neurons and first-order synaptic interconnections. The memory matrix is constructed to store M = αN vectors based on the outer-product learning algorithm. We theoretically prove that, by setting all the diagonal terms of the memory matrix to be M and letting the input error ratio ρ = 0, the probability of successful recall Pr steadily decreases as α increases, but as α increases past 1.0, Pr begins to increase slowly. When 0 < ρ ≤ 0.5, the network exhibits strong error-correction capability if α ≤ 0.15 and this capability is shown to rapidly decrease as α increases. The network essentially loses all its error-correction capability at α = 2, regardless of the value of ρ. When 0 < ρ ≤ 0.5, and under the constraint of Pr > 0.99, the tradeoff between the number of stable states and their attraction force is analyzed and the memory capacity is shown to be 0.15N at best.