Stress-induced Threshold Voltage Shift Research Articles

Physics-Based Compact Model of Current Stress-Induced Threshold Voltage Shift in Top-Gate Self-Aligned Amorphous InGaZnO Thin-Film Transistors

Threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text{T}}$ </tex-math></inline-formula> ) under various current stress (CS) conditions need to be quantitatively studied in self-aligned top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Here, we propose a stretched-exponential function (SEF)-based <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text{T}}$ </tex-math></inline-formula> model that can be applied to various combinations of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{DS}}$ </tex-math></inline-formula> . The proposed model indicates the characteristic electron trapping time constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau _{1}$ </tex-math></inline-formula> is inversely proportional to ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}} - {V}_{\text{T}}$ </tex-math></inline-formula> ). In contrast, the time constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau _{2}$ </tex-math></inline-formula> is directly proportional to the square root of ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{DS}}+{V}_{\text{bi}}$ </tex-math></inline-formula> ), presumably due to the local donor creation by a lateral electric field. The proposed model was verified experimentally in various <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GS}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{DS}}$ </tex-math></inline-formula> configurations. Further, it is confirmed that the lateral electric field dominantly influences donor creation near the drain.

Mechanisms of Carrier Density Increase of Ternary Cation-Based Amorphous Oxide Semiconductors for Thin Film Transistor Applications

Amorphous oxide semiconductor (AOS) thin film transistors (TFTs) based on In2O3 have attracted much interest for use as pixel switching elements in next generation active-matrix liquid crystal (AM-LCD) and active-matrix organic light emitting diode (AM-OLED) displays. The high field effect mobility of In2O3-based AOS devices (10–25 cm2/Vsec) offers significant performance improvements over present-day a-Si TFTs (<1 cm2/Vsec) technology. Additional advantages of AOS materials include low temperature processing (RT–300 °C), isotropic wet etch characteristics, and high optical transparency (>85 % in the visible regime) all of which make this material suitable for large area, flexible, and transparent devices on inexpensive polymer substrates.There have been considerable efforts to incorporate AOSs into devices, particularly in current-driven active matrix displays such as organic light emitting diode displays as pixel-driving switching elements. Strategies to enhance amorphous phase stability, reduce bias stress-induced threshold voltage shifts, and suppress channel carrier densities have been studied and successfully applied to the switching TFT application. Third cation elements are often added to binary cation oxide systems to limit the channel carrier generation for TFT channel application. We have recently reported that the addition of Al to InZnO, a typical binary cation material system leads to enhanced amorphous phase stability, carrier suppression capability and higher carrier mobility, up to ~45 cm2/Vs (Hall Effect mobility) and ~20 cm2/Vs (field effect mobility)1. All of these characteristics are expected to be a key enabler for realizing the next generation ultra-high-definition displays.Post-process annealing is widely employed in AOS-based TFT fabrication since annealing has been shown to improve field effect mobility2-3 and channel/metallization contacts4-5 as well as reduce trap density6, which often leads to unstable device performance or unfavorable hysteresis in their transistor characterstics6-7. However, the post-annealing is often accompanied by an increase in channel carrier density that induces an unfavorable increase in the device off-state current and operation voltages2, 8. To date, the origin of the increase in channel carrier density has not been fully understood.The current study aims to identify the origin of an increase in carrier density after low-temperature annealing conducted in air, particularly for a third-cation AOS system of InAlZnO (IAZO). Through work function investigations and bandgap analysis, the carrier density of IAZO is found to be increased by > 104 times compared to that of unannealed IAZO after low temperature annealing at 200 °C in air. Photoelectron spectroscopic studies reveal that the typical intrinsic (vacancy-based native defect) or extrinsic (cation substitution) doping mechanisms are not the primary cause of the channel carrier increase. From high pressure oxidation with much enhanced reactivity of reaction gases, it is identified that the equilibrium carrier density of IAZO is much higher than those used in typical TFT channel application. The low channel carrier density tends to increase and reach the higher equilibrium carrier density in the absence of kinetic constraints. The combinatorial investigations presented herein help understand the origin of unintentional increase in channel carrier density in amorphous oxides and its effect on the operation of TFTs.The authors gratefully acknowledge the financial supports of the U.S. NSF Award No. ECCS-1931088; the Purdue Research Foundation (Grant No. 60000029); and the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS.References Reed et al. Journal of Materials Chemistry C 2020, 8 (39), 13798-13810.Nomura et al. Applied Physics Letters 2009, 95 (1), 013502.Lee et al. Thin Solid Films 2012, 520 (10), 3764-3768.Shimura et al. Thin Solid Films 2008, 516 (17), 5899-5902.Lee et al. Journal of Applied Physics 2011, 109 (6), 063702.Ide et al. physica status solidi (a) 2019, 216 (5), 1800372.Liu et al. Journal of the American Chemical Society 2010, 132 (34), 11934-11942.Lee et al. Applied Physics Letters 2014, 104 (25), 252103.

Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Annealing atmosphere-dependent electrical characteristics and bias stability of N-doped InZnSnO thin film transistors

The dependence of electrical characteristics and gate bias stress stability of N-doped InZnSnO (IZTO:N) thin film transistors (TFTs) on annealing atmosphere was investigated. The annealing process was performed in air, O2 and N2, respectively, after the deposition of IZTO:N thin film by magnetron sputtering. All annealed IZTO:N films are amorphous and show a high transmittance in the visible light range. The N2-annealed TFT has the highest saturation mobility (μSAT) of 39.5 cm2 V−1s−1 and the lowest subthreshold swing (SS) of 0.40 V/decade. The air-annealed TFT shows similar mobility and SS to the N2-annealed TFT while the O2-annealed TFT shows the lowest mobility and the largest SS. We found that annealing atmosphere has impact on the bias stress stability of the TFTs. Bias stress induced threshold voltage shift of the O2-annealed TFTs is reduced compared to that of air-annealed and N2-annealed TFTs due to the decrease in oxygen vacancy.

Temperature-Dependent Gate Bias Stress Effect in Dioctylbenzothieno[2,3-b]benzothiophene-Based Thin-Film Transistor

We carried out a systematic research on temperature-dependent bias stress instability for Dioctylbenzothieno[2,3-b]benzothiophene-based organic thin-film transistors (OTFTs) below 200 K. 2-D grains boundaries model was employed to analyze the correlation between bias stress effects and the morphologies of first monolayer of the organic film. This enabled us to study the contribution to the shifts of threshold voltage from both grain boundaries and grains/dielectric interface by analyzing the temperature-dependent electrical properties. This paper may deepen our understanding of the bias stress induced threshold voltage shifts influenced by microstructures of the active layer and be helpful to the optimization the designation of poly-crystalline OTFTs.

Grain Size and Interface Dependence of Bias Stress Stability of n-Type Organic Field Effect Transistors.

The effect of grain size and interface dependence of bias stress stability of C60-based n-type organic field effect transistors (OFETs) has been studied. It has been realized that, with increasing grain size of C60, the bias stress induced threshold voltage shift can be controlled and this effect is mainly attributed to the mechanism of charge trapping at grain boundaries. It is further studied that the growth of C60 on the surface of parylene at elevated substrate temperature leads to the creation of radicals at the interface between the active layer and the gate dielectric. These radicals help to improve the bias stress stability of C60-based n-type OFETs. For achieving the bias stress stability, we have presented a procedure of creation of radicals at the interface between C60 and parylene in single gate OFETs instead of dual gate OFETs.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Negative bias temperature instability in p-channel power VDMOSFETs: recoverable versus permanent degradation

In this study, which is aimed at assessing a possible relationship between the recoverable and permanent components of negative bias temperature instability (NBTI) degradation, we investigate NBTI in commercial IRF9520 p-channel VDMOSFETs (vertical double diffused MOSFETs) stressed under particular pulsed bias conditions by varying the pulse on-time while keeping the off-time constant and vice versa. The stress-induced threshold voltage shifts are found to be practically independent of duty cycle when the pulse on-time is kept short or the off-time is kept long, and are found to start increasing with duty cycle only when the on-time is increased or the off-time is decreased beyond specific values. These results, which are discussed in terms of dynamic recovery effects and the mechanisms leading to NBTI degradation, point to the existence of an important correlation between the recoverable and permanent components of degradation.

Detection of Stress-Induced Interface Trap Generation on High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Gated nMOSFETs in Real Time by Stress-and-Sense Charge Pumping Technique

A stress-and-sense charge pumping (SSCP) technique is proposed in this paper to measure the stress-induced interface trap ( $\Delta N_{{\rm {it}}})$ in real-time evolution without stress interruption. Results show that the $\Delta N_{{\rm {it}}}$ measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The $\Delta N_{{\rm {it}}}$ measured by SSCP method after interruption is approximately equal to that by the conventional one. The amount of recoverable $\Delta N_{{\rm {it}}}$ is almost constant and independent of permanent damage. The stress-induced threshold voltage shift ( $\Delta V_{{\rm {th}}})$ and $\Delta N_{{\rm {it}}}$ under various stress frequencies and duty cycles are also measured. The $\Delta V_{{\rm {th}}}$ seems to depend only on the total stress time of stress pulse. The $\Delta N_{{\rm {it}}}$ measured by SSCP with different frequencies and duty cycles is similar. The $\Delta N_{{\rm {it}}}$ also depends on the total stress time of stress pulse, but not the off time during the nonstress half cycle. In addition, it is found that the recovery induced by nonstress half cycle of ac stress is almost negligible as compared with that induced by stress interruption. Moreover, a two-stage phenomenon is observed on $\Delta N_{{\rm {it}}}$ evolution. Results in this paper indicate that the stressing indeed induces trap generation in the first stage.

Gate Bias Stress-Induced Threshold Voltage Shift Effect of a-IGZO TFTs with Cu Gate

The gate bias stress-induced threshold voltage shift effect of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) with Cu gate is investigated in this brief. It is revealed that the Cu-gated TFTs with SiOx gate insulator suffer from serious electrical performance degradation under gate bias stress owing to Cu diffusion into the gate insulator and channel region. A stacked gate insulator of SiOx/SiNx is then proposed to suppress the Cu diffusion. Experimental results show that the Cu-gated TFTs with the stacked gate insulators have a comparable threshold voltage shift effect with that of the conventional TFTs with Mo electrode and SiOx insulator, under both positive and negative gate bias stresses.

The role of metal contacts in the stability of n-type organic field effect transistors

We are presenting a long-time bias stress stability of C60-based n-type organic field effect transistors (OFETs), in bottom gate, top contacts configuration, with aluminium (Al), silver (Ag) and gold (Au) source–drain contacts. The results clearly shows that the bias stress effects in C60-based n-type OFETs is similar to p-type OFETs and it can be reduced by using an appropriate metal for the source–drain contacts. During the bias stress time, the threshold voltage shift and an increase in the contacts resistance have also been measured. On the basis of the stability of the device parameters, it is proposed that the Al source–drain contact-based devices gives better stability as compared to the devices with Ag and Au source–drain contacts. Our results show that the bias stress-induced threshold voltage shift is due to the trapping of charges in the channel region and in the vicinity of the source–drain contacts.

Dynamics of negative bias thermal stress-induced threshold voltage shifts in indium zinc oxide transistors: impact of the crystalline structure on the activation energy barrier

The kinetics of the negative bias thermal stress (NBTS)-induced Vth variations of indium zinc oxide (IZO) transistors with different crystallographic qualities were examined based on the stretched-exponential formalism. A poly-crystalline IZO device had a 0.64 eV lower activation barrier energy than an amorphous IZO device under NBTS conditions. This was attributed to the difference in the migration energy barrier between poly-crystalline and amorphous IZO films. For the recovery process, however, the activation energy barriers (∼0.75 eV) were independent of the crystal structure. A plausible microscopic mechanism to account for the experimental results is proposed.

AC Bias-Temperature Stability of a-InGaZnO Thin-Film Transistors With Metal Source/Drain Recessed Electrodes

In this paper, we fabricated metal source/drain recessed nearly self-aligned amorphous indium-gallium-zinc-oxide thin-film transistors (TFTs) that are highly stable under ac bias-temperature stress (BTS). For TFTs of the size W/L=60 μm/10 μm, the stress-induced threshold voltage shifts are all within -0.35 V. A comprehensive investigation of ac BTS stress polarity, frame time, and duty cycle dependence is presented in the context of high-resolution high-refresh rate active-matrix flat-panel displays. We find that higher frequency bipolar ac pulses increase the device instability. The threshold voltage instability may be reduced significantly by decreasing the duty cycle of the stress waveform.

Bias–stress-induced threshold voltage shift dependence of negative charge trapping in the amorphous indium tin zinc oxide thin-film transistors

Indium tin zinc oxide (ITZO)-based thin-film transistors (TFTs) were fabricated by dc magnetron sputtering in Ar + O2 reactive gas, at room temperature. We present the effect of post-deposition annealing of ITZO thin films on the oxygen vacancies and on the characteristics of TFT devices. When the annealing temperature was increased from room temperature to 350 °C, the resistivity of ITZO film increased from 2.05 × 101 to 2.60 × 103 Ω cm and the interface trap density (Nt) of the TFTs reduced from 3.18 × 1013 to 4.83 × 1011 cm−2. The TFT with the ITZO film which was annealed at 350 °C showed a very small shift in turn-on voltage, even after applying positive bias stress of +12 V for 104 s. The current–voltage characteristics of 350 °C annealing temperature sample indicated that these TFTs were in an enhanced mode of transistor operation with a high on-to-off current ratio of ∼1.26 × 106, high field-effect mobility of 14.17 cm2 V−1 s−1, and low subthreshold slope of 1.23 V/dec. The trapping time reduced from 3720 to 1546 s as the annealing temperature increased from room temperature to 350 °C. These results suggest that thermal annealing played an important role in reducing defects as well as improvement in stability of the TFTs.

Impact of Quantum Confinement on Stress-Induced nMOSFET Threshold Voltage Shift

In this paper, we propose a comprehensive model to express nMOSFET threshold voltage shift induced by stress, ranging from a high tensile one to a high compressive one. Using this model, the quantum confinement effect, combined with large out-of-plane stress, is shown to play an important role to cause the threshold voltage shift as large as about 80 mV induced by high-film-stress contact etch-stop layer.

Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

Bias instability of top-gate amorphous-indium–gallium–zinc-oxide thin-film transistors with source- and drain-offsets is reported. Positive and negative gate bias-stress (VG_STRESS) respectively induce reversible negative threshold-voltage shift (ΔVTH) and reduction in on-current. Migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in the abnormal negative ΔVTH under positive VG_STRESS. The reduction in on-current under negative VG_STRESS is due to increase in resistance of the offsets when positive charges migrate away from the offsets. Appropriate drain and source bias-stresses applied simultaneously with VG_STRESS either suppress or enhance the instability, verifying lateral ion migration to be the instability mechanism.

Stress immunity enhancement of the SiN uniaxial strained n-channel metal–oxide–semiconductor field-effect-transistor by channel fluorine implantation

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to investigate electrical characteristics and stress reliabilities of the n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with HfO2/SiON gate dielectric. Although fluorine incorporation had been used widely to improve device characteristics, however, nearly identical transconductance, subthreshold swing and drain current of the SiN CESL strained nMOSFET combining the CFI process clearly indicates that stress-induced electron mobility enhancement does not affect by the fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with fluorine incorporation obviously exhibits superior stress reliabilities due to stronger Si–F/Hf–F bonds formation. The channel hot electron stress and constant voltage stress induced threshold voltage shift can be significantly suppressed larger than 26% and 15%, respectively. The results clearly demonstrate that combining the SiN CESL strained nMOSFET with fluorinated gate dielectric using CFI process becomes a suitable technology to further enhance stress immunity.

Reliability analysis of MOS varactor in CMOS LC VCO

The paper investigates the reliability of MOS varactor tuned voltage-controlled oscillators (VCO). Due to the stress induced threshold voltage shift of the MOS varactor, the resonant tank degrades and the center frequency and phase noise of VCO deviate. The behavior is modeled and an adaptive body biasing scheme is proposed to make VCO resilient to reliability. In the mean time it does not degrade the VCO performance. An LC VCO at 24GHz carrier frequency with adaptive body biasing is compared with VCO without such biasing design in PTM 65nm technology. The ADS simulation results show that the biasing design helps improve the robustness of the VCO in resonant frequency. The design reduces the frequency sensitivity of VCO by 20% when subjected to threshold voltage degradation.

Electrical stress-induced instability of amorphous indium-gallium-zinc oxide thin-film transistors under bipolar ac stress

Bipolar ac stress-induced instability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors is comparatively investigated with that under a positive dc gate bias stress. While the positive dc gate bias stress-induced threshold voltage shift (ΔVT) is caused by the charge trapping into the interface/gate dielectric as reported in previous works, the dominant mechanism of the ac stress-induced ΔVT is observed to be due to the increase in the acceptorlike deep states of the density of states (DOS) in the a-IGZO active layer. Furthermore, it is found that the variation of deep states in the DOS makes a parallel shift in the IDS-VGS curve with an insignificant change in the subthreshold slope, as well as the deformation of the CG-VG curves.

Bias stress effect in low-voltage organic thin-film transistors

The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.