Implementation Of Stream Cipher Research Articles

Correlation power analysis attack on software implementation of TRIVIUM stream cipher

Power analysis attacks are a category of attacks against cryptographic implementations. In this case, the power consumption of a cryptosystem is analysed to extract its secret values such as secret keys and key streams. This has become a huge threat to modern day cryptosystems. Therefore, identifying cryptographic implementations which are vulnerable to power analysis attacks is very important. Many studies have been carried out on power analysis attacks on block cipher implementations, but relatively less number of studies have been carried out on power analysis attacks on stream cipher implementations. This paper presents a power analysis attack on a software implementation of TRIVIUM stream cipher. In order to analyse the power consumption, correlation power analysis (CPA) is done, and the keystream is successfully recovered.

A VLIW architecture stream cryptographic processor for information security

As an important branch of information security algorithms, the efficient and flexible implementation of stream ciphers is vital. Existing implementation methods, such as FPGA, GPP and ASIC, provide a good support, but they could not achieve a better tradeoff between high speed processing and high flexibility. ASIC has fast processing speed, but its flexibility is poor, GPP has high flexibility, but the processing speed is slow, FPGA has high flexibility and processing speed, but the resource utilization is very low. This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms. By analyzing the structure model, processing characteristics and storage characteristics of stream ciphers, a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented, which has separate/cluster storage structure and is oriented to stream cipher operations. The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths, parallelism among stream cipher processing with different data bit widths, and parallelism among branch control and stream cipher processing with high instruction level parallelism; the designed separate/clustered special bit registers and general register heaps, key register heaps can satisfy cryptographic requirements. So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms. It has been implemented with 0.18μm CMOS technology, the test results show that the frequency can reach 200MHz, and power consumption is 310mw. Ten kinds of stream ciphers were realized in the processor. The key stream generation throughput of Grain-80, W7, MICKEY, ACHTERBAHN and Shrink algorithm is 100Mbps, 66.67Mbps, 66.67Mbps, 50 Mbps and 800Mbps, respectively. The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

A VLIW architecture stream cryptographic processor for information security

As an important branch of information security algorithms, the efficient and flexible implementation of stream ciphers is vital. Existing implementation methods, such as FPGA, GPP and ASIC, provide a good support, but they could not achieve a better tradeoff between high speed processing and high flexibility. ASIC has fast processing speed, but its flexibility is poor, GPP has high flexibility, but the processing speed is slow, FPGA has high flexibility and processing speed, but the resource utilization is very low. This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms. By analyzing the structure model, processing characteristics and storage characteristics of stream ciphers, a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented, which has separate/cluster storage structure and is oriented to stream cipher operations. The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths, parallelism among stream cipher processing with different data bit widths, and parallelism among branch control and stream cipher processing with high instruction level parallelism; the designed separate/clustered special bit registers and general register heaps, key register heaps can satisfy cryptographic requirements. So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms. It has been implemented with 0.18μm CMOS technology, the test results show that the frequency can reach 200MHz, and power consumption is 310mw. Ten kinds of stream ciphers were realized in the processor. The key stream generation throughput of Grain-80, W7, MICKEY, ACHTERBAHN and Shrink algorithm is 100Mbps, 66.67Mbps, 66.67Mbps, 50 Mbps and 800Mbps, respectively. The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

RunStream

We present RunStream, a rapid prototyping framework for realizing stream cipher implementations based on algorithmic specifications and architectural customizations desired by the users. In the dynamic world of cryptography where newer recommendations are frequently proposed, the need of such tools is imperative. It carries out design validation and generates an optimized software implementation and a synthesizable Register Transfer Level Verilog description. Our framework enables speedy benchmarking against critical resources like area, throughput, power, and latency and allows exploration of alternatives. Using RunStream, we successfully implemented various stream ciphers and benchmarked the quality of results to be at par with published hand-optimized implementations.

Performance of Сellular Automata-based Stream Ciphers in GPU Implementation

Earlier the author had developed methods to build high-performance generalized cellular automata-based symmetric ciphers, which allow obtaining the encryption algorithms that show extremely high performance in hardware implementation. However, their implementation based on the conventional microprocessors lacks high performance. The mere fact is quite common - it shows a scope of applications for these ciphers. Nevertheless, the use of graphic processors enables achieving an appropriate performance for a software implementation. The article is extension of a series of the articles, which study various aspects to construct and implement cryptographic algorithms based on the generalized cellular automata. The article is aimed at studying the capabilities to implement the GPU-based cryptographic algorithms under consideration. Representing a key generator, the implemented encryption algorithm comprises 2k generalized cellular automata. The cellular automata graphs are Ramanujan’s ones. The cells of produced k gamma streams alternate, thereby allowing the GPU capabilities to be better used. To implement was used OpenCL, as the most universal and platform-independent API. The software written in C ++ was designed so that the user could set various parameters, including the encryption key, the graph structure, the local communication function, various constants, etc. To test were used a variety of graphics processors (NVIDIA GTX 650; NVIDIA GTX 770; AMD R9 280X). Depending on operating conditions, and GPU used, a performance range is from 0.47 to 6.61 Gb / s, which is comparable to the performance of the countertypes. Thus, the article has demonstrated that using the GPU makes it is possible to provide efficient software implementation of stream ciphers based on the generalized cellular automata. This work was supported by the RFBR, the project №16-07-00542.

High Performance Architecture for LILI-II Stream Cipher

Proposed work presents high performance architecture for LILI-II stream cipher. This cipher uses 128 bit key and 128 bit IV for initialization of two LFSR. Proposed architecture uses single clock for both LFSRs, so this architecture will be useful in high speed communication applications. Presented architecture uses four bit shifting of LFSRD in single clock cycle without losing any data items from function FC. Proposed architecture is coded by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and targeted hardware is Xilinx Virtex5 FPGA having device xc4vlx60, with package ff1148. Proposed architecture achieved throughput of 224.7 Mbps at 224.7 MHz frequency. General Terms Hardware implementation of stream ciphers

Performance and effectiveness of hardware implementation of stream ciphers based on generalized cellular automata

Performance and effectiveness of hardware implementation of stream ciphers based on generalized cellular automata

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Thwarting severe cryptographic hardware attacks requires new approaches to logic and physical designs. This paper presents a systematic design approach to fault tolerant cryptographic hardware designs by combining the concurrent error detection and correction, and uniform switching activity cells. The effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance of stream cipher algorithms with error detection and correction was studied by synthesising the designs on FPGA and custom Integrated Circuits. The hardware building blocks are investigated to minimise switching activity of a circuit for all possible inputs and their transitions by adding redundant gates and increasing the overall number of signal transitions. The overheads of the proposed approach are also discussed.

Key generation based on elliptic curve over finite prime field

With the explosion of networks and the huge amount of data transmitted along, securing data content is becoming more and more important. Data encryption is widely used to ensure security in open networks, like the internet. This paper presents the implementation of stream cipher, where the key stream is generated based on the properties of linear feedback shift register (LFSR) and cyclic elliptic curve (EC) over a finite prime field. Here, the process of encryption/decryption of an image in spatial domain is illustrated and also key file parameters needed for generating the key stream to other parties are encrypted using elliptic curve cryptography (ECC). Only, the encrypted key file parameters are transmitted, not the entire full length key. Since ECC is replacing RSA for key exchange, EC-based stream cipher offers a good choice for encryption in real-time application. The strength of the proposed cipher lies in the generation of random sequence using LFSR over finite prime field and also the use of EC discrete logarithmic problem makes it more difficult to determine the key file parameters. This paper also discusses the security aspects of the proposed cipher which is secure against all kinds of attacks.

Scan-based attacks on linear feedback shift register based stream ciphers

Stream cipher is an important class of encryption algorithm that encrypts plaintext messages one bit at a time. Various stream ciphers are deployed in wireless telecommunication applications because they have simple hardware circuitry, are generally fast and consume very low power. On the other hand, scan-based Design-for-Test (DFT) is one of the most popular methods to test IC devices. All flip-flops in the Design Under Test are connected to one or more scan chains and the states of the flip-flops can be scanned out through these chains. In this paper, we present an attack on stream cipher implementations by determining the scan chain structure of the Linear Feedback Shift Registers in their implementations. Although scan-based DFT is a powerful testing scheme, we show that it can be used to retrieve the information stored in a crypto chip thus compromising its theoretically proven security.

Design and Implementation of Stream Cipher Using Neural Network

The centaral problem in stream cipher cryptograph is the the difficulty to generate a long unpredicatable sequence of binary signals from short and random key. Unpredicatable sequence are desirable in cryptography because it is impossible, given a reasonable segment of its signals and computer resources, to find out more about them. Pseudorandom bit generators have been widely used to construct these sequences. The paper presents a PN sequence generator that uses neural network. Computer simulation tests have been carried out to check the randomness of the generated through statistical tests. There tests have shown the successful PN sequence generator passes all the recommended tests. The paper also proposes and validates the data encryption and decryption process using neural network instead of using traditional methods (Exclusive or). This task increases the difficulty in the breaking the cipher.