Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Abstract

Thwarting severe cryptographic hardware attacks requires new approaches to logic and physical designs. This paper presents a systematic design approach to fault tolerant cryptographic hardware designs by combining the concurrent error detection and correction, and uniform switching activity cells. The effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance of stream cipher algorithms with error detection and correction was studied by synthesising the designs on FPGA and custom Integrated Circuits. The hardware building blocks are investigated to minimise switching activity of a circuit for all possible inputs and their transitions by adding redundant gates and increasing the overall number of signal transitions. The overheads of the proposed approach are also discussed.