ST Microelectronics Research Articles

Ultra low-power, wearable, accelerated shallow-learning fall detection for elderly at-risk persons

This work focuses on the development and manufacturing of a wireless, wearable, low-power fall detection sensor (FDS) designed to predict and detect falls in elderly at-risk individuals. Unintentional falls are a significant risk in this demographic, often resulting from diminished physical capabilities such as reduced hand grip strength and complications from conditions like arthritis, vertigo, and neuromuscular issues. To address this, we utilize advanced low-power field-programmable gate arrays (FPGAs) to implement a fixed-function neural network capable of categorizing activities of daily life (ADLs), including the detection of falls. This system employs a Convolutional Neural Network (CNN) model, trained and validated using the Caffe deep learning framework with data collected from human subjects experiments. This system integrates an ST Microelectronics LSM6DSOX inertial measurement unit (IMU) sensor, embedded with an ultra-low-power Lattice iCE40UP FPGA, which samples and stores joint acceleration and orientation rate. Additionally, we have acquired and published a dataset of 3D accelerometer and gyroscope measurements from predefined ADLs and falls, using volunteer human subjects. This innovative approach aims to enhance the safety and well-being of older adults by providing timely and accurate fall detection and prediction.In this paper, we present an innovative approach to utilizing a compact Convolutional Neural Network (CNN) core for accelerating convolutional operations on a machine learning model, suitable for deployment on an ultra-low power FPGA.

POWERUP PASS MANAGEMENT SYSTEM

This article presents the demonstrator's own application framework for a BLDC motor drive. This demonstration is designed to fulfill the promises made by ST Microelectronics about the R3-PowerUP initiative. As a result, ST devices—particularly the STM32 ARM microcontroller—are employed primarily. The application structure, drivers and peripherals utilized, and the developed cascade control mechanism are all described in the paper. As a consequence, live variables acquired from the MCU are used to display the step responses of both control loops

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency (Fosc) of an N-stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort (g) of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on Fosc of a given N-stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.

Synchronization of scanning probe and pixelated sensor for image-guided diffraction microscopy

A 4-dimensional modality of a scanning transmission electron microscope (4D-STEM) acquires diffraction images formed by a coherent and focused electron beam scanning the specimen. Newly developed ultrafast detectors offer a possibility to acquire high throughput diffraction patterns at each pixel of the scan, enabling rapid tilt series acquisition for 4D-STEM tomography. Here we present a solution to the problem of synchronizing the electron probe scan with the diffraction image acquisition, and demonstrate on a fast hybrid-pixel detector camera (ARINA, DECTRIS). Image-guided tracking and autofocus corrections are handled by the freely-available microscope-control software SerialEM, in conjunction with a high angle annular dark field (HAADF) image acquired simultaneously. The open source SavvyScan system offers a versatile set of scanning patterns, operated by commercially available multi-channel acquisition and signal generator computer cards (Spectrum Instrumentation GmbH). Images are recorded only within a sub-region of the total field, so as to avoid spurious data collection during flyback and/or acceleration periods in the scan. Hence, the trigger of the fast camera follows selected pulses from the scan generator clock gated according to the chosen scan pattern. Software and protocol are provided for gating the trigger pulses via a microcontroller (ST Microelectronics ARM Cortex). We demonstrate the system on a standard replica grating and by diffraction imaging of a ferritin specimen.

Development of n-type epitaxial growth on 200 mm 4H-SiC wafers for the next generation of power devices

Driven by the spread of electric vehicles, the market for SiC power devices is expanding so rapidly that many suppliers are struggling to meet the customer's demand both in terms of final devices and raw material, which nowadays consists of SiC wafers with a diameter of 150 mm (6 in.). STMicroelectronics (ST), world leader in the sale of SiC power device, has reacted by starting the in-house production of the next-generation wafers with a diameter of 200 mm (8 in.). This work describes the optimization of the n-type 4H-SiC epilayers on 200 mm substrates performed by ST in collaboration with LPE® “an ASM company” (LPE). The density of defects and the thickness and doping uniformity of the epilayers grown on 200 mm substrates are characterized, showing results comparable to the ones obtained for standard 150 mm wafers. Also, the reproducibility of the manufacturing process is improved, resulting in a run-to-run variation of the epilayer's thickness and doping below 2%.

Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies

This letter presents a stacked parallel plate (SPP) shunt capacitor (SC) that benefits from metal stack increment with process nodes advancement. It demonstrated high quality (Q) factor and high self-resonance frequency (SRF), promoting the design of analog integrated circuits (IC) in low-cost highly-integrated CMOS technologies at millimeter-wave (mm-wave) frequency range. As a proof-of-concept, an analytical-equation based design method is also proposed and three ac-grounded capacitors: 300-fF, 600-fF and 900-fF, are implemented in STMicroelectronics (STM) 55-nm process. Characterization is performed up to 100 GHz. An effective capacitance density of 0.8 fF/μm2 is obtained. Measurements show Q-values reaching up to 14.7 at 100 GHz and equivalent input series resistances with flat wide band behavior reaching at most an average of 0.55 Ω. SRFs of 140 GHz for the 900-fF SPP-SC up to 368 GHz for the 300-fF SPP-SC are also determined from measurements: the highest SRFs for such large capacitances to the authors’ knowledge.

Integration of a Model Predictive Control with a Fast Energy Management Strategy for a Hybrid Powertrain of a Connected and Automated Vehicle

In the years to come, Connected and Automated Vehicles (CAVs) are expected to substantially improve the road safety and environmental impact of the road transport sector. The information from the sensors installed on the vehicle has to be properly integrated with data shared by the road infrastructure (smart road) to realize vehicle control, which preserves traffic safety and fuel/energy efficiency. In this context, the present work proposes a real-time implementation of a control strategy able to handle simultaneously motion and hybrid powertrain controls. This strategy features a cascade of two modules, which were implemented through the model-based design approach in MATLAB/Simulink. The first module is a Model Predictive Control (MPC) suitable for any Hybrid Electric Vehicle (HEV) architecture, acting as a high-level controller featuring an intermediate layer between the vehicle powertrain and the smart road. The MPC handles both the lateral and longitudinal vehicle dynamics, acting on the wheel torque and steering angle at the wheels. It is based on a simplified, but complete ego-vehicle model, embedding multiple functionalities such as an adaptive cruise control, lane keeping system, and emergency electronic brake. The second module is a low-level Energy Management Strategy (EMS) of the powertrain realized by a novel and computationally light approach, which is based on the alternative vehicle driving by either a thermal engine or electric unit, named the Efficient Thermal Electric Skipping Strategy (ETESS). The MPC provides the ETESS with a torque request handled by the EMS module, aiming at minimizing the fuel consumption. The MPC and ETESS ran on the same Microcontroller Unit (MCU), and the methodology was verified and validated by processor-in-the-loop tests on the ST Microelectronics board NUCLEO-H743ZI2, simulating on a PC-host the smart road environment and a car-following scenario. From these tests, the ETESS resulted in being 15-times faster than than the well-assessed Equivalent Consumption Minimization Strategy (ECMS). Furthermore, the execution time of both the ETESS and MPC was lower than the typical CAN cycle time for the torque request and steering angle (10 ms). Thus, the obtained result can pave the way to the implementation of additional real-time control strategies, including decision-making and motion-planning modules (such as path-planning algorithms and eco-driving strategies).

OpenIPMC: A Free and Open-Source Intelligent Platform Management Controller Software

OpenIPMC is a free and open source firmware designed to operate as an Intelligent Platform Management Controller (IPMC). An IPMC is a fundamental component of electronic boards conformant to the Advanced Telecommunications Computing Architecture (ATCA) standard, currently being adopted by a number of high energy physics experiments, and is responsible for monitoring the health parameters of the board, managing its power states, and providing board control, debug and recovery functions to remote clients. OpenIPMC is based on the FreeRTOS real-time operating system and is designed to be architecture-independent, allowing it to be built for a variety of different Microcontrollers. Having a fully free and open source code is an innovative aspect for this kind of firmware, allowing full customization by the user. In this work we present the features and structure of OpenIPMC and its example implementations on Xilinx Zynq UltraScale+ (ZynqUS+), Espressif ESP32, and ST Microelectronics STM32 architectures.

Modeling and Simulation of Monolithic Single-Supply Power Operational Amplifiers

In this paper a simple PSpice (Personal Simulation Program with Integrated Circuit Emphasis) macro-model was developed, and verified for monolithic power operational amplifiers operated with a single-supply voltage. The proposed macro-model is developed using simplification and build-up techniques for macro-modeling of operational amplifiers and simulates the basic static and dynamic characteristics, including input impedance, small-signal frequency responses at various voltage gains, output power versus supply voltage, slew-rate-limiting, voltage limiting, output offset voltage versus supply voltage ripples, and output resistance. Furthermore, the macro-model also takes into account the ground reference voltage in the amplifier at a single power supply voltage. The model is implemented as a hierarchical structure suitable for the PSpice circuit simulation platform. The sub-circuit is built using standard PSpice components and analog behavioral modeling blocks. The accuracy of the model is verified by extracting the model parameters for single-supply power operational amplifier TDA2005 from ST Microelectronics as example. The effectiveness of the model is validated by comparing the simulation results of the electrical parameters with the corresponding measured values obtained by experimental testing of sample circuits. The comparative analysis shows that the relative error of the modeled large-signal parameters is less than 15%. Moreover, an error of 15% is quite acceptable, considering the technological tolerances of the electrical parameters for this type of analog ICs.

66‐1: High Resolution Quantum Dot Global Shutter Imagers

Quantum dot photodetectors are a promising platform technology that ST Microelectronics has developed, scaled‐up, and is ready to commercialize. Our quantum dot‐based global shutter imagers are responsive from UV to SWIR wavelengths at high resolution, high efficiency, and low dark currents, with good reliability and very competitive cost. Sampling to customers is now ready to start.

Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor

A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm2.mg−1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit.

Design and Development of a Digital Controlled Dielectric Barrier Discharge (DBD) AC Power Supply for Ozone Generation

A digital controlled dielectric barrier discharge (DBD) AC power supply is designed and investigated. The power source design with a diode bridge rectifier and PWM inverter along with driver circuit are presented. A step up transformer is designed to carry 4.6kW and 10 kVp-p for a dielectric barrier discharge (DBD) AC power supply and for ozone generation. An STM (STMicroelectronics) microcontroller is employed to control the phase shift angle of the PWM (Pulse Width Modulation) inverter. The operating frequency of the PWM inverter is 25 kHz. Zero voltage detection can be reached and achieves maximum efficiency. In addition, a high voltage transformer is included The practical results shown that the DBD power supply can be controlled at the chosen value and extreme efficiency can be 87.45 % at 4.6 kW/10 kVp-p.

Iot based water quality monitoring system

The invention discloses an NB-IoT-based water quality monitoring system. The system is a monitoring system developed based on an STM32 platform of the ST Microelectronics. The workflow of the system is divided into three steps: firstly, a temperature sensor and a pH sensor are placed in a solution to be tested, a pH temperature transmitter reads a voltage value in the sensor, converts the voltagevalue into decimal data, and then returns the decimal data into an STM32 main control chip to complete the collection of original data; secondly, the STM32 main control chip obtains a corresponding temperature pH value, and enables a BC28 wireless communication module, connects to a network server, and uploads the data to the server through the BC28 module; and finally, a user logs in a website tocheck the real-time data (temperature, pH value) obtained by the monitoring system and the location of the node, and the user can also select to check the historical data of the node within one month, and the historical data can be displayed to the user in the form of a graph. The NB-IoT-based water quality monitoring system disclosed by the invention can be used for monitoring two indicators ofindustrial wastewater, that is, the temperature and the pH value.

Time Efficient Evaluation of Multi-axis MEMS Gyroscope Using Three-dimensional Test Methodology

Recently, the demand for microelectromechanical systems (MEMS) based inertial sensors has been increased due to a wide range of application in consumer electronics; however, high volume production remains a major challenge for the MEMS industry. This paper proposes a new three dimensional (3-D) test methodology for the time-efficient evaluation of multi-axis MEMS gyroscopes. A mathematical model for the proposed 3-D test method was derived based on the coordinates transformation. The 3-D test methodology was validated experimentally using three-axis MEMS gyroscope from ST Microelectronics and the results were compared with the conventional one dimensional (1-D) test method. The experimental results revealed that the measurement error between the conventional 1-D and the proposed 3-D test was less than 1%, whereas the test time was decreased three times. Finally, the error sources and limitations of the proposed 3-D test method was highlighted.

Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs

ABSTRACTA new digital delay line based on the inverter chain is proposed. The proposed new method of connection of the inverters allows much longer delay times to be achieved for the same number of transistors, the same amount of power to be consumed as for conventional connection of inverters. Simulation results using a 65 nm CMOS design kit from ST Microelectronics are provided. An application example of the proposed delay line is provided for low-power, low-speed successive approximation register (SAR) analogue-to-digital converters (ADC).

VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting

Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelectronics 65-nm technology show that the proposed sensing circuit achieves 807-mV worst case sense margin on average, read access pass yield of $14.4\sigma $ in typical corner and $4.7\times $ reduction in read power compared to conventional voltage sensing.

The Impact of the Virtual Metrology on a Run-to-Run control for a Chemical Mechanical Planarization process

This paper deals with missing and non measured properties for a Chemical Mechanical Planarization (CMP) process in semiconductor manufacturing. A virtual metrology (VM) module is built to estimate non measured properties using a new modified Just-In-Time Learning approach (JITL). The estimated data are integrated thereafter to ensure the smooth functioning of the Run-to-Run (R2R) control loop in order to improve product quality. In collaboration with our industrial partner ST Microelectronics Rousset, the efficiency of the elaborated approach is illustrated using data-set from a CMP process. Then, a comparison is made between estimation quality obtained with the classical and the modified version of JITL approach. The use of estimated data in control context is also presented. For this, another comparison is made for industrial R2R performances using real and estimated data.

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

This paper proposes a fully-digital BIST architecture for the dynamic test of $\Sigma\Delta$ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the $\Sigma\Delta$ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio $\Sigma\Delta$ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.

Analytic Estimation of Thermal Resistance in HBTs

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

Editorial

After nine years (the maximum three consecutive terms) on the Editorial Board of the IEEE TRANSACTIONS on ELECTRON DEVICES (T-ED), Dr. John Tower of Sarnoff Corporation, Prof. Jagadesh Kumar of the Indian Institute of Technology, and Dr. Hervé Jaouen of ST Microelectronics have stepped down from their Editor positions in Image Sensors (John) and MOS Devices and Technology (Hervé and Jagadesh). After six years on the Editorial Board of T-ED, Prof. Adrian Ionescu from the École Polytechnique Fédérale de Lausanne has left his T-ED Editor position in Solid-State Sensors and Actuators. Finally, after three years of service on the T-ED Editorial Board, Dr. David Gundlach of the National Institute of Standards and Technology and Prof. Navakanta Bhat of the Indian Institute of Science have stepped down from their T-ED Editor positions in Molecular and Organic Devices and MOS Devices and Technology, respectively. I would like to express my sincere gratitude—and the gratitude of the Electron Device Society community—to John, Hervé, Jagadesh, Adrian, David, and Navakanta for their commitment, dedication, and hard work during their terms of service. Our very best wishes to them in their future endeavors.