Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor

Abstract

A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm2.mg−1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit.