Stepped Gate Research Articles

Stepped Gate Polysilicon Thin Film Transistor for Large Area Power Applications

ABSTRACTFor the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

Breakdown analysis of an asymmetrical double recessed power MESFET's

FET's with double stepped gate recess are commonly admitted to be presently a very convenient structure capable to overcome the fundamental power limitation related to the breakdown voltage. The present paper deals with an analysis of a double recessed MESFET with a very good and instructive breakdown performance. For the first time we explain on the basis of gate current observations why the double recess structure allows a large breakdown improvement not only at pinch off voltage but also at open channel. Moreover it is shown that the breakdown optimization is fully compatible with the microwave gain performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-Efficiency and Highly Reliable 20 W GaAs Power Field-Effect Transistor in C Band

This paper describes a high-performance and highly reliable GaAs field-effect transistor (FET) with a new gate structure employing the stepped gate recess combined with a multirefractory metal gate. This gate structure allows the simultaneous increase of maximum channel current and gate-drain breakdown voltage (Vgdo) of the FET and thus improves significantly its output power (Po) and power-added efficiency (ηadd). The resultant high Vgdo with highly stable gate Schottky characteristics and a novel surface stabilization prior to plasma-SiN passivation effectively suppress both catastrophic and gradual failures. The four-chip internally matched device (4×12.6 mm) has delivered Po of 20 W at 1 dB gain compression with 39% ηadd over 3.5 to 4.2 GHz. Sufficient reliability of the 20 W device available for satellite use has been assured by comprehensive reliability tests.

A new submicron MOSFET technology with Gate Overlap on Twin Oxide (GOTO) LDD structure

We propose a new self-aligned ITLDD process with minimum gate-drain overlap capacitance by employing a double stepped gate oxide under the overlapped gate and present our device and circuit simulation results to confirm the merits of the proposed gate-drain overlapped structures with respect to reliability and device performance by employing 2-D and 3-D device simulators.

Charge pumping measurements on stepped-gate metal-nitride-oxide-silicon memory transistors

Charge pumping measurements using a variable pulse base level and a constant voltage amplitude are shown to be best suited for the direct determination of surface state densities in the different regions of stepped gate metal-nitride-oxide-silicon memory transistors. The effect of hydrogen annealing on the reduction of the surface state densities in the different regions can be directly demonstrated by using this technique. Finally the technique is very helpful in the study of Write/Erase degradation in these memory devices.