Steering Architecture Research Articles

A 14-bit 1.8-V 20-mW 1-mm/sup 2/ CMOS DAC

A low-voltage low-power small-area and high-resolution digital-to-analog converter (DAC) for mixed-signal applications is Introduced. A binary weighted current steering DAC is a power-efficient architecture, because almost all the current taken from the supply is used for the output signal. The current steering architecture is also highly suitable for high-speed operation. Typically, the architecture suffers from poor linearity characteristics, but the problem can be prevented with a novel calibration method, where the currents generated for the most significant bits are fine tuned. As a result, a very compact and low-power solution can be implemented by using a low-voltage digital technology.

Hybrid electronic fiber optic wavelength-multiplexed system for true time delay steering of phased array antennas

A hybrid electronic fiber optic true time-delay steering architecture is presented which retains the highly hardware compressive property of an earlier all-optical approach and introduces the economical advantages of electronics at every level possible without compromising overall performance. The architecture is particularly suited to large arrays where maximum advantage can be taken of the hardware compression. A detailed design based on this architecture is described for steering a linear, 16-element, <i>L</i>-band (0.7- to 1.4-GHz) array in transmit mode over a scan angle of ±20 deg with a delay resolution of 6 bits (0.63 deg). An analysis of the expected performance of the design is given together with progress toward the fabrication of the prototype system, which includes the first iteration electronic binary delay line subsystem and a single-segment, high-fidelity, directly modulated DFB laser diode fiber optic link. The experimental data from these modules is in agreement with the performance predicted from the analysis.

Hardware-compressive 2-D fiber optic delay line architecture for time steering of phased-array antennas

The requirements for true time steering of phased array antennas are reviewed, and the resulting delay line hardware requirements are discussed. Two hardware-compressive fiber optic delay line architectures are then briefly described and quantitatively compared. The basics of phased array antenna partition are then presented. Based on these principles a delay-compressive and element-compressive 2-D fiber optic delay line architecture is described, and its basic characteristics and capabilities are discussed.