A mathematical procedure is presented as a design/analysis methodology to model computer performance including; (1) Instruction Set Architecture (ISA), (2) specific hardware implementations of the ISAs, and (3) any benchmark program in one closed form solution. Examples are given employing three classical 8 bit processors, and a classical benchmark program, for both CISC and RISC type implementations. The formulation provides a complete solution giving both steady-state and transient results.