Static Phase Error Research Articles

Adaptive phase control of a phase-only spatial light modulator using the Shack-Hartmann wavefront sensor

We present a method to study both static and dynamic phase errors in a phase-only spatial light modulator (SLM) caused by surface irregularities and an imperfect response of each pixel to the applied field. This, in turn, degrades optical reconstruction, particularly in holographic projection applications. The approach uses the Shack-Hartmann wavefront sensor (SHWFS) to measure these errors. A plane wave illuminates the SLM, and the reflected wavefront is measured by the SHWFS and converted into a phase-only computer-generated hologram (CGH). This CGH is displayed on the SLM to compensate for phase errors, which are verified by subsequent wavefront measurements. Experimental results demonstrate the simplicity, robustness to vibration, and real-time capabilities of the SHWFS in contrast to interferometric methods.

Source Switched Charge-Pump PLLs for High-Dose Radiation Environments

This paper presents a radiation tolerant charge-pump Phase-Locked Loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage-or dose-dependent charge injection and address the limitations of Enclosed Layout Transistors (ELTs) in the conventional drain switched charge-pump. The circuit has been processed in a 65nm Complementary Metal Oxide Semiconductor (CMOS) technology and has been experimentally verified with X-rays up to a total ionizing dose of 180 Mrad.

Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch

A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occupies 1.3% of the whole PLL area.

Effect of Phase Errors on a Quantum Control Protocol Using Fast Oscillations

It has been recently shown that fast oscillating control fields can be used to speed up an otherwise slow adiabatic process, making the system always follow an instantaneous eigenvector closely. In applying this method though, one typically assumes perfect phase relations among the control fields. In this work, we discuss the effect of potential static phase errors. We show that the latter can in some cases produce higher fidelities, leading to an unexpected improvement of the method. This is shown numerically and explained via a perturbative expansion of the error produced by the control strategy. When high-precision phase control is accessible, the results suggest that the phases of the control field can be used as free parameters whose optimization can be beneficial for the control protocol.

A programmbale 8-channel multiphase clock generator with 360 phases for focus ultrasound applications

An area efficient, programmable multichannel, multiphase clock generator is proposed to improve the phase resolution for focus ultrasound applications. By using the proposed phase-folding method, the cell amount for generating 360 phases are reduced from 360 to 38 cells. The proposed clock generator is able to provide 360 phases in real-time with 1° phase resolution, 1–51.9% 6-bit DPWM for each channel, and which output frequency varies from 0.1 to 1.5 MHz. Due to the proposed multiphase system is a real-time system, many independent multichannel applications such as focus ultrasound could easily adopt the proposed structure. A new phase-error calibration method for PLL is also present in this paper for reducing the static phase-error due to process voltage and temperature variation. It improves the accuracy of the phase difference in the multiphase system. The proposed ASIC was fabricated in a standard 0.18 μm CMOS process. Measured result shows that multiphase clock generator is able to provide 360 selective phases for each channel. The derived DNL is from −0.106 to +0.108 LSB, and the INL is from −0.284 to +0.449 LSB at 1 MHz.

A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

In this paper, a fast-lock low-power all-digital delay-locked-loop (ADDLL)-based clock generator is proposed that generates fractional multiples of a reference frequency. The proposed clock generator comprises an ADDLL with dual-loop architecture and a fractional frequency multiplier. The coarse tune loop and fine tune loop of the proposed ADDLL can achieve a fast locking time and decrease the static phase error. Moreover, the proposed frequency multiplier can synthesize the 28-phase output clocks of the ADDLL to achieve high multiples. The experimental results demonstrated that the output frequency range of the proposed clock generator was between 176 and 224 MHz, with multiplication factors of 11 ×, 11.5 ×, 12 ×, 12.5 ×, 13 ×, 13.5 ×, and 14 × to cover the very high frequency (VHF) frequency band, where every channel had a bandwidth of 8 MHz. Moreover, the output duty cycle was close to 50% because a divider was used to generate the output signal and the lock time was less than 20 clock cycles. The clock generator was fabricated using a 0.18-μm standard CMOS process, with an active area of 0.59 mm2, power dissipation of 6.7 mW at 224 MHz, and phase noise of − 94.33 dBc/Hz with an offset of 1 MHz. Furthermore, at 176 MHz, the root-mean-square jitter was 25.01 ps, which was less than 0.45% of the output period.

High-contrast imaging at small separations: impact of the optical configuration of two deformable mirrors on dark holes

The direct detection and characterization of exoplanets will be a major scientific driver over the next decade, involving the development of very large telescopes and requires high-contrast imaging close to the optical axis. Some complex techniques have been developed to improve the performance at small separations (coronagraphy, wavefront shaping, etc). In this paper, we study some of the fundamental limitations of high contrast at the instrument design level, for cases that use a combination of a coronagraph and two deformable mirrors for wavefront shaping. In particular, we focus on small-separation point-source imaging (around 1 $\lambda$/D). First, we analytically or semi-analytically analysing the impact of several instrument design parameters: actuator number, deformable mirror locations and optic aberrations (level and frequency distribution). Second, we develop in-depth Monte Carlo simulation to compare the performance of dark hole correction using a generic test-bed model to test the Fresnel propagation of multiple randomly generated optics static phase errors. We demonstrate that imaging at small separations requires large setup and small dark hole size. The performance is sensitive to the optic aberration amount and spatial frequencies distribution but shows a weak dependence on actuator number or setup architecture when the dark hole is sufficiently small (from 1 to $\lesssim$ 5 $\lambda$/D).

A fast-lock and low-power DLL-based clock generator applied for DDR4

This paper presents a fast-lock and low-power delay-locked loop (DLL) circuit applied for DDR4. The proposed modified phase detector and modified charge pump can reduce locking time as well as static phase error. The glitch elimination circuit reduces glitches in the PD for reducing the glitch power. The phase interpolator and phase combiner circuit are used to generate four output frequencies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated through a 0.18-μm standard CMOS process with a supply voltage of 1.8 V. The simulation results indicate that the lock time is less than 20 cycles and the power consumption of the DLL is 15.14 mW at 1.6 GHz. The active die area of the proposed DLL-based clock generator is 0.51 mm2.

High-Resolution Altitude Profiles of the Atmospheric Turbulence with PML at the Sutherland Observatory

The direct detection and characterization of exoplanets will be a major scientific driver over the next decade, involving the development of very large telescopes and requires high-contrast imaging close to the optical axis. Some complex techniques have been developed to improve the performance at small separations (coronagraphy, wavefront shaping, etc). In this paper, we study some of the fundamental limitations of high contrast at the instrument design level, for cases that use a combination of a coronagraph and two deformable mirrors for wavefront shaping. In particular, we focus on small-separation point-source imaging (around 1 $\lambda$/D). First, we analytically or semi-analytically analysing the impact of several instrument design parameters: actuator number, deformable mirror locations and optic aberrations (level and frequency distribution). Second, we develop in-depth Monte Carlo simulation to compare the performance of dark hole correction using a generic test-bed model to test the Fresnel propagation of multiple randomly generated optics static phase errors. We demonstrate that imaging at small separations requires large setup and small dark hole size. The performance is sensitive to the optic aberration amount and spatial frequencies distribution but shows a weak dependence on actuator number or setup architecture when the dark hole is sufficiently small (from 1 to $\lesssim$ 5 $\lambda$/D).

A self‐calibrated delay‐locked loop with low static phase error

SummaryIn conventional delay‐locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D‐type flip flop. The setup time of D‐type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 µm CMOS process design, with a reference frequency of 700 ~ 900 MHz. The active area is 0.031 mm2, and the phase error after correction is less than 5 ps. Copyright © 2015 John Wiley & Sons, Ltd.

Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit

A clock skew-compensation and duty-cycle correction circuit (CSADC) is used as the second-level clock distributing circuit to align a system global clock while maintaining a 50% duty cycle. A power-efficient, range-unlimited, and accuracy-enhanced CSADC, designed mainly with a new delay-interleaving and -recycling technique that mitigates operating frequency limitations while keeping overhead costs low, is proposed in this paper. Our preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18- $\mu $ m CMOS technology. Meanwhile, the lock-in time, static phase error, and power consumption are, respectively, 26 clock cycles, 4.2 ps, and 5.58 mW at 1.75 GHz.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13μm CMOS technology. The frequency synthesizer consumes 8.2mA current from a 1.3V supply voltage and achieves a phase noise of −96.01dBc/Hz @ 1MHz offset from a 2.4GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3μA (0.55%) over the VCO control voltage range of 0.3–1.0V. The closed loop measurements show a minimized static phase error of within ±70ps and a ≃9dB reduction in reference spur level across the PLL output frequency range 2.4–2.5GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations.

A Fast-Locking Digital Delay-Locked Loop with Multiphase Outputs using Mixed-Mode-Controlled Delay Line

This paper proposes a fast-locking digital delay-locked loop (DLL) with multiphase outputs using mixed-mode-controlled delay line (MCDL). The proposed DLL uses a dual-loop technique to control various MOS capacitors and an MOS resistor in the MCDL to improve locking time and reduce static phase error. The chip was fabricated using a 0.35 µm standard CMOS process with a 3.3 V supply voltage. The measurement results showed that the proposed DLL can operate correctly with the input clock frequency varying from 145 MHz to 245 MHz. After the DLL is locked, it can generate four-phase clocks within a single clock cycle. At 180 MHz, the measured root-mean-square jitter and peak-to-peak jitter were 10 ps and 70 ps, respectively. The total power consumption of the DLL was 15 mW, and the active area of the DLL was 0.086 mm 2 . The locking time was less than 30 clock cycles.

A fast‐corrected all‐digital DCC with synchronous input clock

SummaryThis paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd.

A phase-locked loop with background self-calibration for phase error reduction

The proposed phase-locked loop system constructs with the current-mismatch adjusting circuit reduces the static phase error. The proposed current-mismatch adjusting circuit uses a time amplifier circuit to enlarge the phase error between the Up and Dn pulses. The digital code from the current mismatch adjusting circuit calibrates the charge current in the charge pump. The circuit is fabricated in a 0.35 μm CMOS process with 3.3 V supply voltage. The measured static phase error without and with current-mismatch adjusting circuit is 65.41 and 3.44ps, respectively.

A multimode DLL with trade-off between multiphase and static phase error

A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes: mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 μm CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are −18.2 ps, 11.8 ps and −6:44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.

Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers

Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to those of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of -45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.

A delay-locked loop with self-calibration circuit for reducing phase error

A delay-locked loop with self-calibration circuit for reducing phase error is presented. In this DLL, the current mismatch adjusting circuit is proposed in order to reduce the static phase error. To reduce the static phase error the circuit eliminates the mismatch of up/down currents in the charge pump (CP). The current mismatch adjusting circuit is implemented with phase expanded circuit to amplifier the static phase error. To solve the false locking problem, a new phase detector is proposed. The proposed circuit has been fabricated in a 0.18μm CMOS process. The measured static phase errors are without and with calibration circuit are 29ps and 3.89ps at 1.2GHz, respectively.

Phase Noise Modeling for Integrated PLLs in FMCW Radar

The effect of frequency modulation (FM) on the phase noise spectrum of a charge pump phase-locked loop (PLL) for frequency-modulated continuous-wave (FMCW) radar is investigated. The static phase error is calculated as a function of frequency ramp slope and basic PLL design parameters. The phase noise spectrum under FM is deduced from the spectrum in the steady state. Design guidelines for integrated PLLs to be used in FMCW radar are derived from theoretical considerations and experimental results from the literature.