Static Optimizations Research Articles

SYSTEMATIC DESIGN AND EVALUATION OF RECONFIGURABLE ARITHMETIC COMPONENTS IN THE DEEP SUBMICRON DOMAIN

In the era of deep submicron integration, digital design complexity is increasing with rates that are hard to follow. On one hand, market demand for newer, faster and reliable applications never stops. On the other hand, fabrication technology can not cover this demand with frequency increase and dimension shrinking only, as it has been done in the past. Reconfigurable computing is a new design paradigm that takes advantage of idle components or shared functionality between different algorithms, to maximize utilization and improve performance, based on efficient circuit switching interconnections. However, dense and fast switching interconnections bring power dissipation problems, which are more clear in the deep submicron domain. This paper, presents a systematic design methodology, handling performance, area and both dynamic and static power reduction optimizations in the ASIC domain, for a class of reconfigurable arithmetic components, which can be used as IPs in register-transfer level (RTL) and above RTL synthesis methodologies (electronic system level — ESL, high-level synthesis — HLS, IP-based). Both operand bitwidth and technology scaling are explored, showing that the overall proposed architecture offers clear advantages as device dimensions shrink.

Settable and non-interfering signal functions for FRP

Functional Reactive Programming (FRP) provides a method for programming continuous, reactive systems by utilizing signal functions that, abstractly, transform continuous input signals into continuous output signals. These signals may also be streams of events , and indeed, by allowing signal functions themselves to be the values carried by these events (in essence, signals of signal functions), one can conveniently make discrete changes in program behavior by "switching" into and out of these signal functions. This higher-order notion of switching is common among many FRP systems, in particular those based on arrows, such as Yampa. Although convenient, the power of switching is often an overkill and can pose problems for certain types of program optimization (such as causal commutative arrows [14]), as it causes the structure of the program to change dynamically at run-time. Without a notion of just-in-time compilation or related idea, which itself is beset with problems, such optimizations are not possible at compile time. This paper introduces two new ideas that obviate, in a predominance of cases, the need for switching. The first is a non-interference law for arrows with choice that allows an arrowized FRP program to dynamically alter its own structure (within statically limited bounds) as well as abandon unused streams. The other idea is a notion of a settable signal function that allows a signal function to capture its present state and later be restarted from some previous state. With these two features, canonical uses of higher-order switchers can be replaced with a suitable first-order design, thus enabling a broader range of static optimizations.

Assessing the role of U.S. timberland assets in a mixed portfolio under the mean-conditional value at risk framework

This study examines the role of U.S. timberland assets in a mixed portfolio from the risk perspective. Under the mean-conditional value at risk (M-CVaR) optimization framework, the efficient frontier of the mixed portfolio is dramatically improved after adding timberland assets in comparison of the mean-variance (M-V) efficient frontier. The asset allocation strategies formulated by the static and dynamic optimizations indicate that timberland assets maintain a significant allocation in the mixed portfolio. Moreover, risk decomposition is used to identify the risk sources under four different scenarios. It is found that large-cap stocks and small-cap stocks are generally risk intensifiers, whereas treasury bonds, treasury bills, and timberland assets are risk diversifiers.

Tail-constraining stochastic linear–quadratic control: a large deviation and statistical physics approach

The standard definition of the stochastic risk-sensitive linear–quadratic (RS-LQ) control depends on the risk parameter, which is normally left to be set exogenously. We reconsider the classical approach and suggest two alternatives, resolving the spurious freedom naturally. One approach consists in seeking for the minimum of the tail of the probability distribution function (PDF) of the cost functional at some large fixed value. Another option suggests minimizing the expectation value of the cost functional under a constraint on the value of the PDF tail. Under the assumption of resulting control stability, both problems are reduced to static optimizations over a stationary control matrix. The solutions are illustrated using the examples of scalar and 1D chain (string) systems. The large deviation self-similar asymptotic of the cost functional PDF is analyzed.

Efficient data race detection for async-finish parallelism

A major productivity hurdle for parallel programming is the presence of data races. Data races can lead to all kinds of harmful program behaviors, including determinism violations and corrupted memory. However, runtime overheads of current dynamic data race detectors are still prohibitively large (often incurring slowdowns of 10× or more) for use in mainstream software development.In this paper, we present an efficient dynamic race detection algorithm that handles both the async-finish task-parallel programming model used in languages such as X10 and Habanero Java (HJ) and the spawn-sync constructs used in Cilk.We have implemented our algorithm in a tool called TaskChecker and evaluated it on a suite of 12 benchmarks. To reduce overhead of the dynamic analysis, we have also implemented various static optimizations in the tool. Our experimental results indicate that our approach performs well in practice, incurring an average slowdown of 3.05× compared to a serial execution in the optimized case.

Static statistical MPSoC power optimization by variation-aware task and communication scheduling

Corner-case analysis is a well-known technique to cope with occasional deviations occurring during the manufacturing process of semiconductors. However, the increasing amount of process variation in nanometer technologies has made it inevitable to move toward statistical analysis methods, instead of deterministic worst-case-based techniques, at all design levels. We show that by statically considering statistical effects of random and systematic process variation on performance and power consumption of a Multiprocessor System-on-Chip (MPSoC), significant power improvement can be achieved by static software-level optimizations such as task and communication scheduling. Moreover, we analyze and show how the changes in the amount of process variability as well as values of other system constraints affect the achieved power improvement in such system-level optimizations. We employ a mixed-level model of MPSoC critical components so as to obtain the statistical distribution of frequency and power consumption of MPSoCs in presence of both within-die and die-to-die process variations. Using this model, we show that our proposed statistical task scheduling algorithm can achieve substantial power reduction under different values of system constraints. Furthermore, the effectiveness of our proposed statistical task scheduling approach will even increase with the increasing amount of process variation expected to occur in future technologies.

SEEP

In recent years, there has been a rapid evolution of energyaware computing systems (e.g., mobile devices, wireless sensor nodes), as still rising system complexity and increasing user demands make energy a permanently scarce resource. While static and dynamic optimizations for energy-aware execution have been explored massively, writing energyefficient programs in the first place has only received limited attention. This paper proposes SEEP, a framework which exploits symbolic execution and platform-specific energy profiles to provide the basis for energy-aware programming . More specifically, the framework provides developers with information about the energy demand of their code at hand, even for the invocation of library functions and in settings with multiple possibly strongly heterogeneous target platforms. This equips developers with the necessary knowledge to take energy demand into account during the task of writing programs.

Approximate graph clustering for program characterization

An important aspect of system optimization research is the discovery of program traits or behaviors. In this paper, we present an automated method of program characterization which is able to examine and cluster program graphs, i.e., dynamic data graphs or control flow graphs. Our novel approximate graph clustering technology allows users to find groups of program fragments which contain similar code idioms or patterns in data reuse, control flow, and context. Patterns of this nature have several potential applications including development of new static or dynamic optimizations to be implemented in software or in hardware. For the SPEC CPU 2006 suite of benchmarks, our results show that approximate graph clustering is effective at grouping behaviorally similar functions. Graph based clustering also produces clusters that are more homogeneous than previously proposed non-graph based clustering methods. Further qualitative analysis of the clustered functions shows that our approach is also able to identify some frequent unexploited program behaviors. These results suggest that our approximate graph clustering methods could be very useful for program characterization.

Implementing Domain-Specific Languages for Heterogeneous Parallel Computing

Domain-specific languages offer a solution to the performance and the productivity issues in heterogeneous computing systems. The Delite compiler framework simplifies the process of building embedded parallel DSLs. DSL developers can implement domain-specific operations by extending the DSL framework, which provides static optimizations and code generation for heterogeneous hardware. The Delite runtime automatically schedules and executes DSL operations on heterogeneous hardware.

Comparison of Cation Adsorption by Isostructural Rutile and Cassiterite

Macroscopic net proton charging curves for powdered rutile and cassiterite specimens with the (110) crystal face predominant, as a function of pH in RbCl and NaCl solutions, trace SrCl(2) in NaCl, and trace ZnCl(2) in NaCl and Na Triflate solutions, are compared to corresponding molecular-level information obtained from static DFT optimizations and classical MD simulations, as well as synchrotron X-ray methods. The similarities and differences in the macroscopic charging behavior of rutile and cassiterite largely reflect the cation binding modes observed at the molecular level. Cation adsorption is primarily inner-sphere on both isostructural (110) surfaces, despite predictions that outer-sphere binding should predominate on low bulk dielectric constant oxides such as cassiterite (ε(bulk) ≈ 11). Inner-sphere adsorption is also significant for Rb(+) and Na(+) on neutral surfaces, whereas Cl(-) binding is predominately outer-sphere. As negative surface charge increases, relatively more Rb(+), Na(+), and especially Sr(2+) are bound in highly desolvated tetradentate fashion on the rutile (110) surface, largely accounting for enhanced negative charge development relative to cassiterite. Charging curves in the presence of Zn(2+) are very steep but similar for both oxides, reflective of Zn(2+) hydrolysis (and accompanying proton release) during the adsorption process, and the similar binding modes for ZnOH(+) on both surfaces. These results suggest that differences in cation adsorption between high and low bulk dielectric constant oxides are more subtly related to the relative degree of cation desolvation accompanying inner-sphere binding (i.e., more tetradentate binding on rutile), rather than distinct inner- and outer-sphere adsorption modes. Cation desolvation may be favored at the rutile (110) surface in part because inner-sphere water molecules are bound further from and less tightly than on the cassiterite (110) surface. Hence, their removal upon inner-sphere cation binding is relatively more favorable.

Autonomic and Distributed Joint Routing and Power Control for Delay-Sensitive Applications in Multi-Hop Wireless Networks

Multi-hop wireless networks can provide flexible network infrastructures at a low cost. However, most existing wireless networking solutions are designed for delay-insensitive applications, thereby resulting in poor performance when handling delay-sensitive applications. Traditionally, network design problems are formulated as static optimizations, by assuming the network characteristics remain static. However, these solutions are not optimal when the environments are dynamic. Recently, several research works apply machine learning to maximize the performance of multi-hop wireless networks in dynamic environments, but they either only focus on determining policies at the network layer, without considering the lower-layers' actions, or use centralized learning approaches, which are inefficient for delay-sensitive applications, due to the large delay when propagating messages throughout the network. We propose in this paper a new solution that enables the nodes to autonomously determine their routing and transmission power to maximize the network utility, in a dynamic environment. We formulate the problem as a Markov Decision Process, and propose a distributed computation of the optimal policy. Moreover, we use reinforcement-learning to find the optimized policy when the dynamics are unknown. We explicitly consider the impact of the information overhead on the network performance, and propose several novel algorithms to reduce the information overhead.

CoreDet

The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in the execution of multithreaded programs. This severely complicates many tasks, including debugging, testing, and automatic replication. In this work, we avoid these complications by eliminating their root cause: we develop a compiler and runtime system that runs arbitrary multithreaded C/C++ POSIX Threads programs deterministically. A trivial non-performant approach to providing determinism is simply deterministically serializing execution. Instead, we present a compiler and runtime infrastructure that ensures determinism but resorts to serialization rarely, for handling interthread communication and synchronization. We develop two basic approaches, both of which are largely dynamic with performance improved by some static compiler optimizations. First, an ownership-based approach detects interthread communication via an evolving table that tracks ownership of memory regions by threads. Second, a buffering approach uses versioned memory and employs a deterministic commit protocol to make changes visible to other threads. While buffering has larger single-threaded overhead than ownership, it tends to scale better (serializing less often). A hybrid system sometimes performs and scales better than either approach individually. Our implementation is based on the LLVM compiler infrastructure. It needs neither programmer annotations nor special hardware. Our empirical evaluation uses the PARSEC and SPLASH2 benchmarks and shows that our approach scales comparably to nondeterministic execution.

CoreDet

The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in the execution of multithreaded programs. This severely complicates many tasks, including debugging, testing, and automatic replication. In this work, we avoid these complications by eliminating their root cause: we develop a compiler and runtime system that runs arbitrary multithreaded C/C++ POSIX Threads programs deterministically. A trivial non-performant approach to providing determinism is simply deterministically serializing execution. Instead, we present a compiler and runtime infrastructure that ensures determinism but resorts to serialization rarely, for handling interthread communication and synchronization. We develop two basic approaches, both of which are largely dynamic with performance improved by some static compiler optimizations. First, an ownership-based approach detects interthread communication via an evolving table that tracks ownership of memory regions by threads. Second, a buffering approach uses versioned memory and employs a deterministic commit protocol to make changes visible to other threads. While buffering has larger single-threaded overhead than ownership, it tends to scale better (serializing less often). A hybrid system sometimes performs and scales better than either approach individually. Our implementation is based on the LLVM compiler infrastructure. It needs neither programmer annotations nor special hardware. Our empirical evaluation uses the PARSEC and SPLASH2 benchmarks and shows that our approach scales comparably to nondeterministic execution.

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications

Exploiting runtime memory access traces can be a complementary approach to compiler optimizations for the energy reduction in memory hierarchy. This is particularly important for emerging multimedia applications since they usually have input-sensitive runtime behavior which results in dynamic and/or irregular memory access patterns. These types of applications are normally hard to optimize by static compiler optimizations. The reason is that their behavior stays unknown until runtime and may even change during computation. To tackle this problem, we propose an integrated approach of software [compiler and operating system (OS)] and hardware (data access record table) techniques to exploit data reusability of multimedia applications in Multiprocessor Systems on Chip. Guided by compiler analysis for generating scratch pad data layouts and hardware components for tracking dynamic memory accesses, the scratch pad data layout adapts to an input data pattern with the help of a runtime scratch pad memory manager incorporated in the OS. The runtime data placement strategy presented in this paper provides efficient scratch pad utilization for the dynamic applications. The goal is to minimize the amount of accesses to the main memory over the entire runtime of the system, which leads to a reduction in the energy consumption of the system. Our experimental results show that our approach is able to significantly improve the energy consumption of multimedia applications with dynamic memory access behavior over an existing compiler technique and an alternative hardware technique.

Structure and dynamics of the water films confined between edges of pyrophyllite: A first principle study

Edge sites of clay minerals play a key role for pH dependent sorption of ions from solutions of electrolytes. Pyrophyllite, Al 2[Si 4O 10](OH) 2, is an important structural prototype for a variety of 2:1 dioctahedral phyllosilicates but in contrast to the other clays has no permanent structural charge. The structure of thin water films confined between most common edges of 1Tc pyrophyllite: (0 1 0), (1 1 0) and (1 0 0), was analyzed by means of ab initio molecular dynamic simulations. The system setup allowed for a full flexibility of the interfaces and a proton exchange between the edges of pyrophyllite and water molecules in solution. The structure of hydrated surfaces is compared with the recent predictions of static geometry optimizations for edge-vacuum interfaces. All surfaces studied reveal a strong hydrophilic character of edge similar to the hydrated silica surface and the facets of simple layered hydroxides. Spontaneous proton transfer between different surface sites were observed in molecular dynamics simulations of the (0 1 0) interface. The proton bound to the Si OH site was found to exchange with the Al OH group by the mechanism Si OH + Al OH ↔ Si O - + Al OH 2 + . The direction of the proton transfer agrees with the scale of relative proton affinities for surface sites obtained from the static calculations. Alternatively, the proton attached to the Al OH 2 site exchanges with the Al OH group. In both reactions, the protons are transferred through the chains of hydrogen bonds formed between water molecules in the solution and the surface sites. The observed mechanisms might be one of the basic schemes for the surface proton diffusion in compacted clays. Kinetics of the proton transfer at edge sites is limited by the rate of rearrangements of the water molecules near interface.

A Combined Experimental and Theoretical Evaluation of the Structure of Hydrated Microporous Aluminophosphate AlPO4-18

Water adsorption in the microporous aluminophosphate AlPO4-18 is studied by a combination of solid-state NMR, X-ray diffraction, and density functional theory calculations. The change of the framework structure upon hydration is moderate, and NMR gives local information on the environment of Al and P atoms. The structural distribution of water molecules in the channels has been explored by a combination of first-principle molecular dynamics simulations and of static geometry optimizations. Two starting points have been considered for the calculations. If the structure of the dehydrated aluminophosphate is used, the simulation result is not satisfactory with an incomplete hydration and no agreement with NMR results. Starting from a partial refinement of the aluminophosphate framework for the hydrated system, a structure with six tetrahedral and six octahedral Al atoms in the unit cell is obtained, involving twelve water molecules coordinated to Al atoms and twelve others in the channels, and in good agreement with experimental data.

Molecular Dynamics of a Vanadate−Dipeptide Complex in Aqueous Solution

Static geometry optimizations and Car-Parrinello molecular dynamics simulations with the BP86 density functional, as well as NMR chemical shift calculations at the GIAO-B3LYP level, have been used to assess structure, speciation, and dynamics of aqueous solutions of the vanadate-glycylglycine complex. According to the simulations, this complex should be formulated as five-coordinate, anionic [VO2(GlyGly')]- (GlyGly' = H2N-CH2-C(O)-N-CH2-CO2). The neutral conjugate acid is unstable in water, where it is deprotonated within a few picoseconds. Six-coordinate structural alternatives, [VO(OH)2(GlyGly')]-, are disfavored energetically and/or entropically. The hydration shell around [VO2(GlyGly')]- in water is characterized in terms of suitable pair correlation functions.

RENO

RENO is a modified MIPS R10000 register renamer that uses map-table "short-circuiting" to implement dynamic versions of several well-known static optimizations: move elimination, common subexpression elimination, register allocation, and constant folding. Because it implements these optimizations dynamically, RENO can apply optimizations in certain situations where static compilers cannot. Several of RENOýs component optimizations have been previously proposed as independent mechanisms. Unified renaming [13] implements dynamic move elimination and speculative memory bypassing [19] (the dynamic counterpart of register allocation). Register integration [21] implements common-subexpression elimination and speculative memory bypassing. RENO unifies these mechanisms and adds a dynamic version of constant folding, RENOCF. RENOCF uses an extended map table format and a limited form of dynamic operation fusion. Cycle-level simulation shows that RENO dynamically eliminates (i.e., optimizes away) 22% of the dynamic instructions in both SPECint2000 and MediaBench. RENOCF is responsible for 12% and 17% of the eliminations, respectively. Because dataflow dependences are collapsed around eliminated instructions, performance improves by 8% and 13%, respectively. Alternatively, because eliminated instructions do not consume issue queue entries, physical registers, or issue, bypass, register file, and execution bandwidth, RENO can be used to absorb the performance impact of a significantly scaled-down execution core.

Static and dynamic locality optimizations using integer linear programming

The delivered performance on modern processors that employ deep memory hierarchies is closely related to the performance of the memory subsystem. Compiler optimizations aimed at improving cache locality are critical in realizing the performance potential of powerful processors. For scientific applications, several loop transformations have been shown to be useful in improving both temporal and spatial locality. Recently, there has been some work in the area of data layout optimizations, i.e., changing the memory layouts of multidimensional arrays from the language-defined default such as column-major storage in Fortran. The effect of such memory layout decisions is on the spatial locality characteristics of loop nests. While data layout transformations are not constrained by data dependences, they have no effect on temporal locality. On the other hand, loop transformations are not readily applicable to imperfect loop nests and are constrained by data dependences. More importantly, loop transformations affect the memory access patterns of all the arrays accessed in a loop nest and, as a result, the locality characteristics of some of the arrays may worsen. This paper presents a technique based on integer linear programming (ILP) that attempts to derive the best combination of loop and data layout transformations. Prior attempts to unify loop and data layout transformations for programs consisting of a sequence of loop nests have been based on heuristics not only for transformations for a single loop nest but also for the sequence in which loop nests will be considered. The ILP formulation presented here obviates the need for such heuristics and gives us a bar against which the heuristic algorithms can be compared. More importantly, our approach is able to transform memory layouts dynamically during program execution. This is particularly useful in applications whose disjoint code segments demand different layouts for a given array. In addition, we show how this formulation can be extended to address the false sharing problem in a multiprocessor environment. The key data structure we introduce is the memory layout graph (MLG) that allows us to formulate the problems as path problems. The paper discusses the relationship of this ILP approach based on the memory layout graphs to other work in the area including our previous work. Experimental results on a MIPS R10000-based system demonstrate the benefits of this approach and show that the use of the ILP formulation does not increase the compilation time significantly.

Cacheminer: A runtime approach to exploit cache locality on SMP

Exploiting cache locality of parallel programs at runtime is a complementary approach to a compiler optimization. This is particularly important for those applications with dynamic memory access patterns. We propose a memory-layout oriented technique to exploit cache locality of parallel loops at runtime on Symmetric Multiprocessor (SMP) systems. Guided by application-dependent and targeted architecture-dependent hints, our system, called Cacheminer, reorganizes and partitions a parallel loop using the memory-access space of its execution. Through effective runtime transformations, our system maximizes the data reuse in each partitioned data region assigned in a cache, and minimizes the data sharing among the partitioned data regions assigned to all caches. The executions of tasks in the partitions are scheduled in an adaptive and locality-presented way to minimize the execution time of programs by trading off load balance and locality. We have implemented the Cacheminer runtime library on two commercial SMP servers and an SimCS simulated SMP. Our simulation and measurement results show that our runtime approach can achieve comparable performance with the compiler optimizations for programs with regular computation and memory-access patterns, whose load balance and cache locality can be well optimized by the tiling and other program transformations. However, our experimental results show that our approach is able to significantly improve the memory performance for the applications with irregular computation and dynamic memory access patterns. These types of programs are usually hard to optimize by static compiler optimizations.