State Assignment Method Research Articles

Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states.

State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Different strategies for the combination of merging and splitting transformation procedures for incompletely specified finite state machines implemented on field-programmable logic devices are offered. In these methods, such optimization criteria as the speed of operation, power consumption and implementation cost are considered already in the early phase of finite state machine synthesis. The methods also take into account the technological features of programmable logic devices and the state assignment method. The transformation quality ratio is calculated on the base of estimations of consumed power, critical path delay and number of utilized logic cells. The user is also able to choose the order of merging and splitting procedures and the direction of the optimization by setting weights for each criterion. The methods of the estimation of optimization criteria values are described, and the experimental results are also discussed.

Grain evolution simulation of ceramic tool material in spark plasma sintering process based on an improved cellular automata model

In this paper, a mathematical model for simulating the grain evolution process of ceramic materials was constructed to investigate the effects of the sintering parameters on the microstructure in the spark plasma sintering process. Firstly, a new algorithm of removing the right angle of grain was improved and an improved cell state assignment method was proposed based on the cellular automata model. Then the sintering parameters were coupled into the model, and the simulation method of grain growth and pore evolution were proposed. Finally, a ceramic material grain evolution model with stomata structure for spark plasma sintering was constructed. The simulation results showed that the grain size increased exponentially with the increases of holding time and sintering temperature, while the pores gradually decreased with the increase of the two parameters and the density of the material. Besides, the uniformity of grain growth also decreased with the increase of holding time. These results conformed to the topological characteristics of grain growth and the law of grain boundary migration, and can provide support for the sintering parameters optimization of ceramic tool materials.

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

As the development of deep-submicron and nano-technology, leakage power minimisation becomes as important as dynamic power reduction in IC design. In order to achieve low-power state assignment for finite-state machine (FSM) synthesis, a multi-population genetic algorithm (MPGA)-based state assignment method is proposed. MPGA consists of an outer-loop and a set of inner-GAs. In MPGA, inner-GA is a local search component for finding low-power state assignment. Selection, crossover and mutation are used to perform variations on individuals. Cost function is defined based on power dissipation formulation of complementary metal oxide semiconductor (CMOS) gate for dynamic power and leakage power estimation. The outer-loop is used to optimise the parameters of inner-genetic algorithm (GA) through population variation schema, intra-specific competition and newborn. Twenty-three FSMs that were commonly used as benchmarks are employed to test the effectiveness of MPGA and compare different state assignment methods. Experimental results show MPGA achieves a significant improvement over the previous publications both on dynamic power and leakage power reduction in most benchmarks.

State assignment method for improvement of transient response caused by controller switching

Abstract In this paper, the suppression of undesirable transient responses caused by controller switching is considered. In some cases, we switch the feedback and the observer gains in order to improve the control performance. However, such switching causes large disturbed transient response. To suppress such undesirable transient response, we propose to assign the state of the dynamical controller. This paper shows that it can be further suppressed by attaching an observer in order to suppress the transient response caused by switching, even in the case that all the states can be measured directly. The proposed assignment rule is based on the observability gramian of the post-switching closed loop system.

A multi-population evolution stratagy and its application in low area/power FSM synthesis

Finding a low area/power state assignment is a NP-hard problem in finite-state machines synthesis. In order to solve this problem, this study proposes a multi-population evolution strategy, denoted as MPES. MPES accomplishes the task by using inner-ES and outer-ES. In inner-ES, subpopulations evolve separately and are responsible for local search in different regions. Alternating (μ + λ) strategy and (μ, λ) strategy are employed to select parental individuals from the ranked population for mutation. Three mutation operators, ‘replacement’, ‘2-exchange’ and ‘shifting’, perform on the parental individuals to generate offspring. Different fitness functions are defined for area and power evaluation, respectively. Outer-ES acts as a shell to optimize the subpopulations of inner-ES for better and better solutions. In outer-ES, the parameters of evolving subpopulations are represented by individuals of outer-population. Outer-ES performs selection and mutation on the outer-population to change the parameters of evolving subpopulations in inner-ES for generating better solutions. Two assistant operators, competition and newborn, work together for poor subpopulations elimination and creating new subpopulations. By using two-level ES, MPES is able to obtain multiple good solutions. We test the MPES extensively on benchmarks, and compare it with previous state assignment methods from various aspects. The experimental results show MPES achieved a significant cost reduction of area and power dissipation over the previous publications.

Complex minimization method for finite state machines implemented on programmable logic devices

A complex method for the minimization of finite state machines (FSMs) implemented on Programmable Logic Devices (PLDs) is proposed. In this method, such optimization criteria as the cost of implementation, power consumption, and speed of operation are taken into account already at the stage of minimizing internal states. It also makes it possible to take into consideration the parameters of technology of integrated circuits and the state assignment method. In addition, the proposed method allows one to minimize the number of transitions and input variables of the FSM. The method is based on sequential merging of two internal states. For this purpose, the set of all pairs of states that can be merged is found, and the pair that best satisfies the optimization criteria is chosen for merging. Algorithms for the estimation of optimization criteria values are described, and some features of the computer implementation of the proposed method are discussed.

Synthesis of finite state machines for CPLDs

Synthesis of finite state machines for CPLDsThe paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

State assignment and logic optimization for finite state machines

An FSM synthesis for PAL-based CPLDs is presented in the paper. A new approach consisted of the original method of the state assignment and PAL-oriented multi-level optimization is proposed. The aim of the proposed heuristic method is oriented on the area minimization. Presented state assignment method takes into consideration elements of two-level minimization, while the essence of PAL-oriented multi-level optimization is to search for multi-output implicants that can be shared by several functions. Results of experiments prove the effectiveness of the method for CPLD structures consist of PAL-based logic blocks.

Correct Charge State Assignment of Native Electrospray Spectra of Protein Complexes

Correct charge state assignment is crucial to assigning an accurate mass to supramolecular complexes analyzed by electrospray mass spectrometry. Conventional charge state assignment techniques fall short of reliably and unambiguously predicting the correct charge state for many supramolecular complexes. We provide an explanation of the shortcomings of the conventional techniques and have developed a robust charge state assignment method that is applicable to all spectra.

Assignment of polar states for protein amino acid residues using an interaction cluster decomposition algorithm and its application to high resolution protein structure modeling

We have developed a new method (Independent Cluster Decomposition Algorithm, ICDA) for creating all-atom models of proteins given the heavy-atom coordinates, provided by X-ray crystallography, and the pH. In our method the ionization states of titratable residues, the crystallographic mis-assignment of amide orientations in Asn/Gln, and the orientations of OH/SH groups are addressed under the unified framework of polar states assignment. To address the large number of combinatorial possibilities for the polar hydrogen states of the protein, we have devised a novel algorithm to decompose the system into independent interacting clusters, based on the observation of the crucial interdependence between the short range hydrogen bonding network and polar residue states, thus significantly reducing the computational complexity of the problem and making our algorithm tractable using relatively modest computational resources. We utilize an all atom protein force field (OPLS) and a Generalized Born continuum solvation model, in contrast to the various empirical force fields adopted in most previous studies. We have compared our prediction results with a few well-documented methods in the literature (WHATIF, REDUCE). In addition, as a preliminary attempt to couple our polar state assignment method with real structure predictions, we further validate our method using single side chain prediction, which has been demonstrated to be an effective way of validating structure prediction methods without incurring sampling problems. Comparisons of single side chain prediction results after the application of our polar state prediction method with previous results with default polar state assignments indicate a significant improvement in the single side chain predictions for polar residues.

B09: State assignment method for high speed FSMS

The state assignment method of the finite state machines for PAL-based structures is presented. The limited number of product terms (k-AND-gates) that are connected to a single sum (OR-gate) causes, that function which is the sum of p-implicants, when p >k, is built of more than one cell. Automatically the number of logic levels of such realization increases. The main idea of solving this problem is to count the number of product term during the process of state assignment, and add additional bits to a codingword if needed. In one of the most basic states of the logic synthesis, the elements referring to restrictions of PAL-based devices and elements of two-level minimization are taken into account.

Synthesis for logical initializability of synchronous finite-state machines

Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, X) simulator. In practice, commercial logic and fault simulators often require initialization under such a three-valued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensure the logical initializability of synchronous finite-state machines. The method includes both state assignment and combinational logic synthesis steps. It is shown that a previous approach to synthesis-for-initializability, which uses a constrained state assignment method, may produce uninitializable circuits. Here, a new state assignment method is proposed that is guaranteed correct. Furthermore, it is shown that combinational logic synthesis also has a direct impact on initializability; necessary and sufficient constraints on combinational logic synthesis are proposed to guarantee that the resulting gate-level circuits are logically initializable. The above two synthesis steps have been incorporated into a computer-aided design tool, SALSIFY, targeted to both two-level and multilevel implementations.

State Assignment of the Finite State Machine for PLD-Implementation

The paper proposes a method of state assignment for PLD-based FSM. This method is aimed at obtaining a combinational component of FSM in the swn-of-products (SOP) fonn of a Boolean ftmctions system with the number of product terms in each fimction, which does not exceed a given value. Procedures of rmding encoding variables and reducing the code length are introduced.

Performance-driven synthesis in controller-datapath systems

This paper describes new algorithms which combine state assignment and pipelining to perform timing-driven synthesis. A cycle time requirement for a controller-datapath system must be satisfied under fixed arrival times of datapath outputs and departure times of datapath inputs. As a result, the controller's design must take into account not only cycle time of the FSM in isolation, but also input arrival time specifications and output departure time requirements. Most state assignment methods minimize area; moreover, state assignment alone may not be sufficient to eliminate all delay bottlenecks. Performance-Driven Synthesis (PDS) applies both high-level and sequential optimizations to meet a cycle time requirement: we use new don't-care assignment algorithms to minimize the delays of FSM output signals on critical paths by reducing their dependencies on late-arriving FSM primary input signals; we also use new pipelining algorithms to break critical paths which cannot be fixed by state assignment. Experimental results show that PDS improves delays with little area overhead.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Binary decision based representation implementation of sequential systems

Two methods of binary decision based representation and implementation of asynchronous sequential systems are considered. A method of state assignment for the binary decision based system is presented. The method is based on the weights of the test variables and their effect on BD graph complexity.

Methods for Synthesizing Testable Sequential Circuits

We present three approaches to designing testable sequential machines. (Testability, in the present context, refers to the ability to generate tests. Testable synthesis guarantees high fault coverage by using an automatic test generator.) In the first approach, we develop a partial scan method in which scan flip-flops are selected to break up the cyclic structure of the sequential circuit. In the second approach, we present a novel state assignment method that results in reduced feedback or pipeline-like structure. The third approach, also applicable to finite state machines, embeds a suitably designed test machine in the given specification before synthesis.

A State Assignment for p‐Valued Sequential Machines

AbstractFor p‐valued synchronous sequential machines a new method of state assignment is proposed. In this method, a given sequential machine is expressed by a state transition table and then codes with low Hamming weight are assigned to the internal states with high frequency of appearance. This process yields the state transition functions which express transition to the states with low frequency of appearance, thereby attaining the state transition functions with the minimum number of terms in the principal disjunctive canonical form. All the procedures can be expressed in a simple straightforward algorithm and therefore can be processed fast. Experiments on a computer for p = 3 show that the truth‐table densities of the state transition matrices are about 80 to 90 percent compared with those obtained by the triangle method [1, 2] which is one of the existing methods. The results compare favorably with those obtained by other methods even after simplification by the extended Quine‐McCluskey method.

Pass-transistor asynchronous sequential circuits

Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N+M times.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficiency of state assignment methods for PLA-based sequential circuits

The implementation of finite sequential machines by using a programmable array logic to synthesise their combinational part is considered. A critical view of the efficiency of existing methods to carry out the state assignment of these machines is given, and it is shown that we can derive a bound on the number of state variables beyond which even an arbitrary coding usually leads to better results in terms of area occupation. It is suggested in the paper that this bound can still be found when more refined area estimates are used.