Complex minimization method for finite state machines implemented on programmable logic devices

Abstract

A complex method for the minimization of finite state machines (FSMs) implemented on Programmable Logic Devices (PLDs) is proposed. In this method, such optimization criteria as the cost of implementation, power consumption, and speed of operation are taken into account already at the stage of minimizing internal states. It also makes it possible to take into consideration the parameters of technology of integrated circuits and the state assignment method. In addition, the proposed method allows one to minimize the number of transitions and input variables of the FSM. The method is based on sequential merging of two internal states. For this purpose, the set of all pairs of states that can be merged is found, and the pair that best satisfies the optimization criteria is chosen for merging. Algorithms for the estimation of optimization criteria values are described, and some features of the computer implementation of the proposed method are discussed.