Standby Power Research Articles

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

Inrush current suppression technology for floating nuclear power plants based on connecting Pre-T in series

For floating nuclear power plants, the inrush current produced under no-load closing situations of the working transformer (T) is necessary to be suppressed. Since the pre-magnetization technology of connecting small capacity pre-magnetized transformer (Pre-T) in series is simple to realize and can be used as the standby power source, it has a great application prospect. In this paper, the inrush current peak value which may be generated during each switch-closing step is analytically analyzed, and the suppression mechanism is concluded that: In the first two steps, the inrush current is suppressed because of the high equivalent resistance and leakage reactance of the windings of Pre-T. During the pre-magnetization process, the actual steady-state flux of T is gradually established. When its amplitude and phase are pre-synchronized with the expected steady-state flux of the power source, it is switched into the system without any inrush current generated. On this basis, guiding functions are constructed to select the best parameters of Pre-T and the switch-closing control strategies. Based on the optimal parameters, the simulation model is built by MATLAB/Simulink software. Simulation results show that the proposed method has a prominent inrush current suppression effect without closing angle control. It has high robustness under the conditions of typical remanent flux in the iron core and certain dispersion of the circuit switches. Moreover, it significantly accelerates the differential protection operation speed when the transformer is closed under internal faults.

Influence of storage on mission success probability of m-out-of-n standby systems with reusable elements

Recent studies have shown that elements reusing through preventive replacements is beneficial in enhancing the mission success probability (MSP) of standby systems. While storage is often an essential unit for system functions, none of the existing works on standby systems with reusable elements have considered this unit in the system modeling and analysis. We make contributions by modeling and optimizing a m-out-of-n standby system with reusable elements and an imperfect storage unit. The system performs a mission task that must satisfy a pre-specified demand during the mission time. Surplus product produced by operating elements is stored; in the case of not meeting the demand, the storage unit, if available, supplies the saved product to compensate the deficiency. All the system elements, during their idle time, may undergo different types of actions including staying in the warm standby mode, being protected, undergoing imperfect or perfect maintenance. A probabilistic modeling approach is first proposed for assessing the MSP of the considered system. The optimal operation and maintenance schedule (OMS) problem is then formulated and solved, which determines the OMS maximizing the MSP. A case study on a standby power generation system is provided to demonstrate influences of several storage parameters (storage capacity, storage reliability, and storage activation procedure reliability) on the MSP and optimized OMS solutions.

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

Countermeasures against Static Power Attacks

In recent years it has been demonstrated convincingly that the standby power of a CMOS chip reveals information about the internally stored and processed data. Thus, for adversaries who seek to extract secrets from cryptographic devices via side-channel analysis, the static power has become an attractive quantity to obtain. Most works have focused on the destructive side of this subject by demonstrating attacks. In this work, we examine potential solutions to protect circuits from silently leaking sensitive information during idle times. We focus on countermeasures that can be implemented using any common digital standard cell library and do not consider solutions that require full-custom or analog design flow. In particular, we evaluate and compare a set of five distinct standard-cell-based hiding countermeasures, including both, randomization and equalization techniques. We then combine the hiding countermeasures with state-of-the-art hardware masking in order to amplify the noise level and achieve a high resistance against attacks. An important part of our contribution is the proposal and evaluation of the first ever standard-cell-based balancing scheme which achieves perfect data-independence on paper, i.e., in absence of intra-die process variations and aging effects. We call our new countermeasure Exhaustive Logic Balancing (ELB). While this scheme, applied to a threshold implementation, provides the highest level of resistance in our experiments, it may not be the most cost effective option due to the significant resource overhead associated. All evaluated countermeasures and combinations thereof are applied to a serialized hardware implementation of the PRESENT block cipher and realized as cryptographic co-processors on a 28nm CMOS ASIC prototype. Our experimental results are obtained through real-silicon measurements of a fabricated die of the ASIC in a temperature-controlled environment using a source measure unit (SMU). We believe that our elaborate comparison serves as a useful guideline for hardware designers to find a proper tradeoff between security and cost for almost any application.

Extending the lifetime of NVM

Recently, Non-Volalile Memory (NVM) technology has revolutionized the landscape or memory systems. With many advantages, such as non volatility and near zero standby power consumption, these byte-addressable memory technologies are taking the place of DRAMs. Nonetheless, they also present some limitations, such as limited write endurance, which hinders their widespread use in today's systems. Furthermore, adjusting current data management systems to embrace these new memory technologies and all their potential is proving to be a nontrivial task. Because of this, a substantial amount of research has been done, from both the database community and the storage systems community, that tries to improve various aspects of NVMs to integrate these technologies into the memory hierarchy. In this tutorial we survey state-of-the-art work on deploying NVMs in database and storage systems communities and the ways their limitations are being handled within these communities. In particular, we focus on the challenges that are related to low write endurance and extending the lifetime of NVM devices.

A scalable platform for investigating the space-specific features of the temporal energy usage pattern and saving potential with real-time bigdata

The Korean government has initiated a “Green New Deal” policy, in which a smart energy platform was proposed for more efficient building energy management that could monitor energy consumption in real time and control electrical installation and appliance in a timely manner. With the energy bigdata collected via IoT-based smart energy meter, this study aimed to develop a scalable platform for investigating the space-specific features of the temporal energy usage pattern and the relevant energy saving potential by electrical installation (i.e., lighting, electrical appliances, heating & cooling systems) in a building. This study was conducted in four stages: (i) real-time bigdata collection; (ii) development of dashboard; (iii) scalable analysis of energy usage pattern; and (iv) scalable analysis of energy saving potential. Main finding can be summarized as follow. First, more than 50% of the energy usage in main spaces (i.e., classrooms) was consumed by the heating & cooling systems. Second, the total energy saving potential was estimated at 11.50% when applying the developed actuator to the standby power and electrical radiator. Third, the annual cost saving potential as economic feasibility was estimated at 11.13%. The proposed scalable platform can contribute to investigating the energy usage pattern by electrical installation from a spatio-temporal perspective and to changing the occupants’ behaviors for energy savings by considering space-specific features and occupancy patterns. The proposed novel approach can be extended to various types of buildings.

On High-Temperature Galvanic Elements of Stand­by Power Supply Sources based on Energy Condensed Systems

Study of ignition, combustion and electrochemical processes occurring in thin multilayer high-temperature galvanic elements derived from low-gas energy condensed systems was carried out. The research results made it possible to design a wide range of multifunctional standby power supply sources with improved performance, differing in application types, initiation modes, activation and operation times, overall dimensions and shape.

Robust Low Power Transmission Gate (TG) based 9T SRAM cell with Isolated Read and Write Operation

Stability and performance of conventional SRAM cells operating at low voltages are severely affected due to enhanced process variations. This paper proposes a Transmission Gate (TG) based 9T SRAM cell with independent read/write operation and compares its performance with 6T, 8T, and 10T SRAM cells. The enhanced read and write ability of the cell is due to the selective use of positive feedback loop. To show the efficacy of the proposed technique, simulations are carried out using 130nm UMC technology files on Cadence Virtuoso and HSPICE. The transistor size with minimum length and width is used in each configuration using the UMC 130nm technology file for all the simulations. Various body biasing techniques (Reverse Body Bias and Forward Body Bias) are applied to reduce active and standby power. It has been observed that the proposed cell shows better results in terms of enhanced read, write and hold stability and for reduced power also. Further, the write access time is less for the proposed cell. The layout of the proposed architecture is also shown.

Stability of a Fe-Rich Cathode Catalyst in an Anion Exchange Membrane Fuel Cell

Fe-rich alloys have been widely studied as catalyst materials for the cathodic oxygen reduction reaction (ORR) in hydrogen fuel cells, and many have shown high activities. The stability of Fe-rich catalysts has also been researched, and some studies have shown promising results using an accelerated stress test (AST), which uses a potential cycling method. However, for commercial fuel cell applications, such as standby power systems, the catalyst has to tolerate a high potential for a long period, which can not be represented by the AST test. In this paper, the cathode stability of a Fe-rich catalyst was studied using a standby cell potential of 0.9V, a potential shown to be challenging for the competing Pt catalysts. After 1500 hrs of testing, significant morphology changes of both the tested cathode and anode were found due to a Fe leaching process. Other alloy materials, including Ni, Cr, and Mn, were also found leached out along with the Fe species from the catalyst framework. The results are a cautionary note for using Fe based catalysts for AEMFC cathodes.

Reduction of Reactive Power Waste of Inductive Electrical Appliances using Power Factor Correction

Electricity is the primary source of power in most countries including Sri Lanka, and saving or minimising the waste of it has become crucial in facing the world power crisis. Electrical power is wasted in various ways including reactive power waste due to induction and capacitance of appliances, and standby power loss. These two contribute most to the waste. This paper focuses on reducing the reactive power waste of inductive electrical appliances commonly used in home and office by increasing the power factor. An attempt was made to reduce the power waste of inductive electrical appliances by connecting a capacitor bank with a variable capacitance in parallel with the appliance. Optimal capacitance and the power factor are determined using the capacitor bank. Results indicate about 30 percent of power saving could be achieved for fluorescent tube lamps using a power factor correction. A maximum power factor of 0.93 is achieved at the capacitance value of 2.99 F. It is not possible, by this method, to increase the power factor of more capacitive equipment such as CFL bulbs and ceiling fans. In this case, power minimisation could be tried connecting inductors in parallel with the equipment. Power factor and power consumption of home electrical appliances were measured for advising the general public of high power consuming equipment, especially in stand-by mode. To attain a further reduction of power waste it is proposed to measure inductance, capacitance and resistance of appliances using Hendry, Farad and Ohm meter. Total impedance can then be calculated and the power waste could be minimised using appropriate capacitors and/or inductors. Keywords: reactive power, power factor, power waste, reactive power waste, power minimisation

Implementing an Algorithm for Locating Complex Zeros of Analytical Functions in the Complex Plane

Ghost loads (also known as phantom loads, vampire loads, standby power or leaking electricity) needlessly consume electricity when electronic devices are not in use, costing institutions money and needlessly sending tons of CO2 into the atmosphere. An analysis of computer and other ghost loads at the University of Colorado Colorado Springs (UCCS) was conducted in the Spring of 2009 with the results showing that computers annually cost the school $37,505.96-$45,017.56. The environmental impact of idle computers was calculated as 521.73-626.07 tons of CO2 emitted into the atmosphere. These estimates are likely low since data was neither gathered on weekends, nor during the summer. Other potential sources of ghost loads are identified and strategies that could lead to lower costs and carbon emissions are presented.

Design of analog nonlinear transformations based on a Gilbert multiplier for energy detection

This paper focuses on the design of two analog nonlinear transformations dedicated to analog signal processing such as energy detection: the square function and the Teager Energy Operator (TEO). Both requiring an analog multiplier, this paper firstly analyses the design equations of a MOS Gilbert cell in order to operate around the mid supply voltage. Considering this, an analog multiplier, having a differential input range of ±400 mV, has been designed using an AMS 0.35 μm technology and a voltage supply (VDD) of 3.3 V. It has a core area of 620 μm2 and offers power-gating capability, which enables a power consumption of 2.28 μW when a duty cycle of 0.25% is considered. Next, an analog square function and an analog TEO, have been implemented and manufactured using the designed Gilbert cell. The analog square function has a core area of 0.9 mm2 and measurement results show that it is able to compute the square value of its differential input voltage with a mean precision of 2.92% in 5 μs assuming a differential input voltage of ±400 mV with a common voltage of VDD/2. Moreover, it generates 700 mV spikes when 200 mV pulses are applied on its input. Finally, the designed analog TEO has been implemented using its discrete time equation instead of its continuous time equation since it does not require derivatives computing. It has a core area of 2.2 mm2, an active power consumption of 6.21 mW and a standby power consumption of 1.43 nW. Measurement results shows that it generates until 250 mV spikes when 200 mV pulses are applied on its input.

Quality and Reliability-Exploitation Modeling of Power Supply Systems

This article describes the issues related to the analysis of the reliability-exploitation of power supply systems in transport telematics devices (PSSs in TTDs). This paper characterizes solutions, which are applied in supply systems, and describes a PSS in a TTD from a main source and a standby one. This enables determining the dependencies denoting the probabilities of the system staying in full ability state, safety threat state, and safety unreliability state. A quality analysis of the PSS in TTD was conducted, and the indicator value of the supply continuity quality was evaluated. This indicator allows the demonstration of continuity quality of power supply (CQoPS) dependency on many quality dimensions, not just reliability. An example demonstrates the calculation of CQoPS factor for both the main and the standby power supply, employing three observations, each influencing the quality. The presented considerations in the field of quality and reliability-exploitation modeling of a PSS can be applied as well in other public utility facilities (including those classified as critical infrastructure). The character of functions performed by critical infrastructure facilities demands an operating continuity of these systems at an appropriate level. The co-first authors of the article once again address the issue of determining CQoPS factor, this time on the basis of modeling using mathematical evidence. TTD is an example in this article, because the presented methods can be used in any kind of system, especially in the power source of critical systems.

Reliability improvement of IGZO‐TFT in hybrid process with LTPS

AbstractAn AMOLED panel using hybrid backplane technology based on p‐type low temperature polycrystalline silicon (p‐LTPS) and n‐type indium–gallium–zinc–oxide (n‐IGZO) thin‐film transistors (TFTs) has been successfully manufactured. New pixel and Gate‐on‐Array (GOA) circuits were designed and fabricated using this technology. GOA with CMOS inverter is realized by utilizing both IGZO and p‐LTPS. The hybrid backplane AMOLED panel can operate between 1 and 120 Hz, which enables both high refresh rate and low standby power display applications. Furthermore, the AMOLED panel lifetime has markedly enhanced by improving IGZO TFT's uniformity and reliability.

Research and Analysis of Phase Modulation Method of Standby Power Transmission Line Based on TSPST

When the power plant fails, in order to reduce the excessive inrush current generated by the switching of the backup power supply to the electrical equipment, the backup power supply was unable to switch quickly. This article mainly studies and analyzes a power supply method based on TSPST to adjust the phase of the standby power transmission line and make corresponding design and calculation for the theory and structure of the process. According to the actual parameters of the project, the power supply method is simulated and analyzed. According to simulation experiments, the feasibility and reliability of the proposed power supply method are verified.

7‐1: Distinguished Paper: Reliability Improvement of IGZO‐TFT in Hybrid Process with LTPS

An AMOLED panel using hybrid backplane technology based on p‐type LTPS and n‐type oxide has been successfully manufactured. New pixel and Gate‐on‐Array (GOA) circuits were designed and fabricated using this technology. CMOS operation of the GOA is realized by utilizing both IGZO and p‐LTPS. The hybrid backplane AMOLED panel can operate between 1 Hz and 120 Hz, which enables both high refresh rate and low standby power display applications. Furthermore, the AMOLED panel lifetime has markedly enhanced by improving IGZO TFT's uniformity and reliability.

High-Efficiency Lighting Systems With Advanced Controls

The adoption of LED modules coupled with advanced control systems allows a high level of performance both for occupant's satisfaction and for energy performance. The article describes the lighting design process and highlights that the impact of controls on the energy performance can be very high. A complete case study of a lighting system renovation implemented in a library room is shown. The library was divided in different zones. In each zone, the optimal control was adopted. Energy results demonstrated improvements in energy savings and performance via the proposed means. The energy performances measured before the renovation and after the renovation were 72 and 8.5 kW h/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per year, respectively, with a saving of more than 70%. The article introduces a double-level on/off switch, one based on the soft BUS control and the other based on deep switch of the power circuit that allows saving of the standby power during the long off-time and increases the reliability. The article highlights the importance of postinstallation phases, which concern parameter programming and optimization. Only because of a careful measurement and monitoring system it is possible to optimize operation of the automatic control systems and to implement the Plan-Do-Check-Act (PDCA) approach.

Status of Microgrid Protection and Related Standards and Codes: Protection Supports Integration

Microgrids are becoming a significant aggregation of distributed energy resources (DERs) that improves the reliability and resilience of the power delivery system. Most of the early microgrid experience occurred in behind-themeter applications for installations with critical loads and significant backup power and load prioritization requirements. Very successful systems that include campus and utility applications have been operational for up to and exceeding a decade. For these early systems, available codes and standards consisted mostly of adapted device-level legacy emergency and standby power requirements. Grid interconnection and efficient, safe operating requirements were improvised via programmed computers, and the protection focus was the microgrids themselves. The larger microgrid installations often required qualified staff trained to monitor and operate the systems.

Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current IREAD variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.