Standby Power Consumption Research Articles

Yield enhancement of a 16.6 cm/sup 2/ monolithic large-area integrated multiprocessor system using laser reconfiguration

A 16.6 cm/sup 2/ monolithic large-area integrated multiprocessor system comprising nine identical programmable video signal processing elements was reconfigured by excimer laser-formed connections and discontinuities of conductor lines in a redundant bus system. The total yield enhancement of processors using laser reconfiguration amounts to 13.3%. On the prototypes, up to six processors per chip were functional at 66 MHz, providing a peak arithmetic performance of 6 GOPS per multiprocessor system. The power supply to defective processors with a high stand-by power consumption was terminated by laser, leading to a halving of power consumption. Furthermore, for the improvement of the laser process, vertical links between two metallization levels were formed on two chips with different standard CMOS layer sequences on special test structures. For the yield statistics of the formed vertical links, a contact resistance R/sub K/ larger than 3 /spl Omega/ was treated as a failure. With the laser processing of vertical links with an area of 14/spl times/14 /spl mu/m/sup 2/, a yield of 100% has been achieved. Beyond those, conventional accelerated life time tests were performed to examine the reliability of laser-formed vertical links. In microelectronic systems, a failure rate of 10 FIT/layer in 11.4 years corresponding to 0.1% failures is accepted. An extrapolation of Black's equation to operating conditions (100/spl deg/C, 2.5 mA) resulted in a failure rate of 0.1% in a time of 39 years.

Corona-plasma triggered pseudospark discharges

This paper reports on a novel pseudospark triggering technique using a corona-plasma electrode to feed initial electrons into one of the pseudospark hollow electrodes. This corona-plasma trigger can be used either at the cathode or anode side of the pseudospark, and it can be connected as well to the high voltage electrode as to the grounded one. With this trigger scheme, a pseudospark switch working at pulse repetition frequencies (PRF) up to 100 Hz has been demonstrated in a continuous mode of operation, while PRF as high as 1 kHz has been achieved in a burst mode. The cumulative number of pseudospark discharges triggered with this technique is already above 5*10/sup 7/, and this corona-plasma triggered pseudospark is still in operation without performance degradation. The main advantage of this pseudospark triggering technique lies in its simultaneous simplicity and reliability allowing high repetition rate, long lifetime, and the complete absence of keep-alive electrode and standby power consumption.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Scaling the Si metal-oxide-semiconductor field-effect transistor into the 0.1-μm regime using vertical doping engineering

Conventional scaling of the Si MOSFET into the deep submicron regime requires high substrate doping levels. This extracts a severe speed penalty, if lower standby power consumption (i.e., good subthreshold behavior) is to be maintained. We explore the scaling of fully depleted silicon-on-insulator (SOI) structures, and show, both analytically and by numerical simulation, how the horizontal leakage is controlled by vertical doping engineering. Our analysis allows different structures to be evaluated in terms of a natural length scale indicating good subthreshold behavior. Finally, we describe how retrograde doping may be used to mimic the SOI concept in bulk Si. Our results show good subthreshold behavior in the deep submicron regime can be achieved without large junction capacitance, high threshold voltage, or heavy channel doping.

An Intelligent Chilled Mirror Humidity Instrument

An intelligent, chilled mirror humidity instrument has been designed for use on buoys and ships. Our design goal is for the instrument to make high-quality dewpoint temperature measurements for a period of up to one year from an unattended platform, while consuming as little power as possible. The instrument uses a General Eastern Dew-10 chilled mirror sensor and is controlled by an onboard digital processor that is programmable in BASIC. Communications to an external logger are provided by an RS-232 compatible interface. The housing is made of PVC and is approximately 76 cm long × 11.5 cm in diameter; the complete instrument weight is 5.8 kg. Energy consumption is typically 800 J per measurement; standby power consumption is 0.05 W. A series of dockside tests have been carried out to evaluate the long-term accuracy and reliability of the D10IQ. As a standard, we used an EG&G 200M Dewtrak chilled mirror instrument that was cleaned manually at frequent intervals. We found that the mean difference between the D10IQ and EG&E 200M was roughly 0.9°C, which is within the expected error of our calibration procedure, and that the standard deviation of the difference was about 0.8°C. The variance is contributed equally by a fast time scale random fluctuation and a 5- to 10-day period variation. For our purpose it is most significant that there was very little calibration drift of the D10IQ so long as the mirror reflectance stayed above a well-defined and readily monitored threshold value. Thus it appears that the D10IQ can provide a fairly reliable and accurate means for measuring humidity from unattended platforms.

A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architecture

A 1-Mb dynamic RAM has been fabricated using 1.2-/spl mu/m double-level metal CMOS technology. A novel divided bitline matrix architecture allows the conventional double-polysilicon planar memory cell to be used without sacrificing signal-to-noise (S/N) ratio or die efficiency. Optimized for high bandwidth, the device uses static column circuitry and a 256K/spl times/4 organization to achieve data rates >180 Mb/s at worst-case voltage and temperature conditions. The 5.97-mm/spl times/11.4-mm die incorporates a flexible laser blown fuse link redundancy scheme which can repair a wide variety of fabrication defects. Typical row access and cycle times are 85 and 190 ns, respectively, achieving >21-Mb/s bandwidth in the non-optimized row access mode. Although some DC power is dissipated in static circuitry, active power consumption has been kept to 225 mW (45 mA), and standby power consumption has been reduced to 2.5 mW (0.5 mA).

An implantable current souce for electrical nerve stimulation.

A CMOS bipolar voltage controlled current source is described which due to its low part count lends itself very well to integration in a thin film hybrid circuit. The standby power consumption is less than 400 μW.

Nonvolatile static read/write memory cell using CMNOS structure

A new type of nonvolatile static read/write memory cell constructed with three MOS transistors and one MNOS transistor is proposed. The MNOS transistor and one of the MOS transistors involved are complementary combined to offer binary states in the Λ-shaped <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> curve for memory operation under normal power supply. Upon power failure, the MNOS transistor acts as a back-up element for nonvolatility. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.

A Small, Low Power Pulse Height Analyzer with Memory for Space Applications

A space flyable multichannel analyzer with 4096 × 16 bit memory has been developed. This paper is concerned primarily with the instrument's operational characteristics and unique thick-film construction. Foremost in the analyzer's specifications are a 200 milliwatt standby power consumption, typical differential linearity of ±0.2% over 98% of full scale, and physical dimensions of 3.25H × 8.0W × 6.75D.