Standard Logic Process Research Articles

Reliability of pFET EEPROM With 70-Å Tunnel Oxide Manufactured in Generic Logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.

Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset

An ultra low dark current pixel has been developed for embedded active-pixel complementary metal oxide semiconductor (CMOS) image sensors using a standard CMOS logic process. Conventional CMOS image sensors suffer from high dark current as a result of the high interface state density at the field oxide edge. In the proposed novel pixel, the photo-sensing diode is surrounded by a ring-shaped poly-silicon reset gate which isolates the photo-sensing area from the field oxide edge. Hence, the dark current level can be effectively reduced. However, in the novel pixel, the large overlap capacitance between the reset poly-gate ring and the sensing node can severely affect the output swing. To optimize this novel pixel, the poly-silicon gate is limited to isolate the photo-sensing area from the field oxide edge. Furthermore, a constant bias voltage applied to the poly-silicon gate provides an additional advantage of extended dynamic range. The effects of technology scaling on the pixel performance are investigated as well.

Multilevel vertical-channel SONOS nonvolatile memory on SOI

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.