Standard Complementary Metal-oxide Semiconductor Technology Research Articles

Near Infrared Efficiency Enhancement of Silicon Photodiodes by Integration of Metal Nanostructures Supporting Surface Plasmon Polaritrons

Recent years have witnessed a growing interest in detectors capable of detecting single photons in the near-infrared (NIR), mainly due to the emergence of new applications such as light detection and ranging (LiDAR) for, e.g., autonomous driving. A silicon single-photon avalanche diode is surely one of the most interesting and available technologies, although it yields a low efficiency due to the low absorption coefficient of Si in the NIR. Here, we aim at overcoming this limitation through the integration of complementary metal-oxide-semiconductor (CMOS) -compatible nanostructures on silicon photodetectors. Specifically, we utilize silver grating arrays supporting surface plasmons polaritons (SPPs) to superficially confine the incoming NIR photons and therefore to increase the probability of photons generating an electron-hole pair. First, the plasmonic silver array is geometrically designed using time domain simulation software to achieve maximum detector performance at 950 nm. Then, a plasmonic silver array characterized by a pitch of 535 nm, a dot width of 428 nm, and a metal thickness of 110 nm is integrated by means of the focused ion beam technique on the detector. Finally, the integrated detector is electro-optically characterized, demonstrating a QE of 13% at 950 nm, 2.2 times higher than the reference. This result suggests the realization of a silicon device capable of detecting single NIR photons, at a low cost and with compatibility with standard CMOS technology platforms.

High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block (CAB) system for field-programmable analog array (FPAA). The proposed architecture is based on the complementary metal-oxide semiconductor (CMOS) transistor level design where MOSFET transistors operating in the saturation region are adopted. The proposed CAB architecture is designed to implement six of the widely used current mode operations in analog processing systems: addition, subtraction, integration, multiplication, division, and pass operation. The functionality of the proposed CAB is demonstrated through these six operations, where each operation is chosen based on the user’s selection in the CAB interface system. The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations. Furthermore, optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells. Moreover, these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design. Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35 μm standard CMOS technology. The design uses a V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 . This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article. Consequently, the proposed design has a clear aspect of simplicity, low power consumption, and high bandwidth operation, which makes it a suitable candidate for mobile telecommunications applications.

CMOS compatible manufacturing of a hybrid SET-FET circuit

This study analyzes feasibility of complementary metal–oxide–semiconductor (CMOS)-compatible manufacturing of a hybrid single electron transistor–field effect transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar (NP) with embedded Si nanodot generated by ion-beam irradiation. The integration process from NPs to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated NPs. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.

Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review

AbstractThis paper presents a systematic analytical comparison of the single‐Miller capacitor frequency compensation techniques suitable for three‐stage complementary metal–oxide–semiconductor (CMOS) operational transconductance amplifiers (OTAs). The comparison is carried out with the aid of a figure of merit that expresses a trade‐off among gain‐bandwidth product, load capacitance, and total transconductance, for equal values of the phase margin. The results found can be used before the transistor‐level design step and provide useful guidelines for the optimization of the small‐signal performance. Simulations by using a 65‐nm standard CMOS technology confirming the effectiveness of the theoretical comparison for 10 different OTA topologies are also provided.

ECONOMIC SIGNIFIANCE AND DESIGN OF LOW AREA AND LOW POWER MAGNITUDE COMPARATOR

Multibit digital comparators take up large surface and high power consumption. As they are composed of logic gates, it is recommended to decrease the number of transistors in the logic gates using different transistor logics. By decreasing the number of transistors, the occupied surface and power consumption of the entire circuit will also decrease. The identical circuit was propounded applying standard CMOS (Complementary MetalOxide-Semiconductor) technology and with a combination of PTL (Pass Transistor Logic) and DVL (Dual Value Logic) transistor logics. Due to less area and decreased number of transistors, the physical design (layout) of the whole circuit will become easier and less time consuming from layout designer point of view, then in case of standard CMOS technology. As an output load was used a 1fF capacitance for both circuits. Correspondingly, the propounded circuit cuts down the power consumption by 21.3%, the delay was decreased by 28.4%, and the number of transistors was reduced by 25%. The circuit was developed using Custom Compiler tool. All the simulations are done using Synopsys Hspice and WaveView tools. SAED (Synopsys Armenia Educational Department) 32/28 nm technology process libraries have been used during the work.

Broadband and compact silicon mode converter designed using a wavefront matching method.

A broadband and compact TE0-TE1 mode converter for a mode division multiplexing system designed using a wavefront matching method is realized. We present the first experimental demonstration of a silicon waveguide device designed by a wavefront matching method. In order to achieve broadband operation of the silicon mode converter, seven wavelengths are considered in its optimization process. The designed silicon mode converter is fabricated via a standard complementary metal-oxide-semiconductor technology, which enables low-cost mass production. Measurements performed using the fabricated mode converter correlate strongly with the calculated results.

From Charge to Spin and Spin to Charge: Stochastic Magnets for Probabilistic Switching

As the rapid pace of Moore's Law has been slowing down, there has been intense activity to “reinvent the transistor.” An emerging paradigm is to complement the existing complementary metal-oxide-semiconductor (CMOS) technology with new functionalities, rather than finding a drop-in replacement for it. In this article, we discuss such a complementary approach that we call probabilistic spin logic (PSL) based on the concept of a probabilistic or p-bit. p-bits fluctuate between 0 and 1 and can be imagined in between deterministic bits that are either 0 or 1 and quantum bits that are a superposition of 0 and 1. Interconnected circuits built out of p-bits (p-circuits) can be broadly useful for machine learning and quantum computing in the solution of problems that conventional CMOS may not be particularly suited for. Although such p-bits can be implemented using standard CMOS technology, we will show that the inherent physics of nanomagnets can naturally provide an energy efficient and scalable p-bit implementation through the use of low-barrier magnetic tunnel junctions (MTJs). In this article, we provide a general description of p-bits and p-circuits and discuss their applications. We review experimental progress toward constructing p-bits and p-circuits exploiting the inherent stochasticity of nanomagnets, from a physics/device/circuits perspective. In particular, we identify building blocks for “write” and “read” operations that can be used in different combinations to construct functional p-bits and p-circuits. Finally, we discuss the prospects and challenges of PSL as an emerging, unconventional computing paradigm for a beyond CMOS era.

Analysis of electroluminescence spectra from high optical-power density forward-biased silicon-led in standard CMOS technology

A Si-LED with high-power density p+-n junction and wedge-shaped electrodes was fabricated by standard complementary metal oxide-semiconductor (CMOS) process, and its electroluminescence (EL) spectra were measured at different forward currents. By studying the EL spectra, two interesting phenomena were found. One was that the main peak of EL spectra transited from long wavelength (1135 nm) to short wavelength (1078 nm) along with the forward current increased. The other was that two light emission peaks with energy larger than band gap (Eg) were observed. For the first time, reasonable explanations to the two phenomena were given. Here, the peak shift is attributed to that, with forward current increased, the electron-hole pair recombination of the bound excitons without assist of phonons, increases faster than that of those bound or free excitons with assist of phonons. And the existence of two energy-high light emission peaks is resulted from that, under strong electric field, hot holes absorb one or two phonons from the crystal lattice and then recombine with electrons in conduction band.

First Near-Ultraviolet- and Blue-Enhanced Backside-Illuminated Single-Photon Avalanche Diode Based on Standard SOI CMOS Technology

We present the world's first backside-illuminated (BSI) single-photon avalanche diode (SPAD) based on standard silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. This SPAD achieves a good dark count rate (DCR) after backside etching, comparable to DCRs of BSI SPADs fabricated on bulk wafers. Unlike bulk-wafer-based BSI SPADs, which typically suffer from poor violet and blue sensitivity, the proposed BSI SPAD features increased near-ultraviolet sensitivity as well as significant sensitivity in the violet and blue spectral ranges, thanks to the ultrathin-body SOI. To the best of our knowledge, this is the best result ever reported for any BSI SPAD in the standard CMOS technology. In addition, it also shows high sensitivity at long wavelengths thanks to the interface between silicon and silicon-dioxide layers. Therefore, it achieves a photon detection probability over 26% at 500 nm and 10% in the 400-875 nm wavelength range at 3 V excess bias voltage. The timing jitter is 119 ps full width at half maximum at the same operation condition at 637 nm wavelength. For the proposed BSI SPAD, the buried oxide layer in SOI wafers is used as an etching stop during the wafer backside-etching process, and therefore it ensures the excellent performance uniformity in large arrays.

Direct integration of piezoactuator array with active-matrix oxide thin-film transistors using a low-temperature solution process

The integration of a thin-film piezoelectric actuator with standard CMOS (Complementary Metal-Oxide-Semiconductor) technology has attracted many practical interests for totally integrated smart devices such as electronics, microfluidics, sensors and actuators. However, the major obstacle of the integration lies in high annealing temperature required for crystallization of piezoelectric thin-films (600–750 °C), which leads to degradation of back circuitry. This paper reports, for the first time, a successful direct integration of lead-zirconium-titanate (PZT) thin-film, the piezoelectric with the greatest commercial applicability, with an active-matrix oxide thin-film transistor (TFT) using a low-temperature (450 °C) solution-processable PZT thin-film. The actuation of the PZT actuator array, electrically driven by the active-matrix TFT, was confirmed. The proposed device can be used in various applications such as micropumps/valves, microfluidic control, energy harvesting, sensors and the like.

An Efficient Forward-Biased Si CMOS LED With High Optical Power Density and Nonlinear Optical-Power-Current Characteristic

A forward-biased silicon-based light-emitting device (Si-LED) was designed and fabricated by standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology without any modification. For the Si-LED, wedge-shaped electrodes and needle-like tip were designed to enhance the intensity of electric field. When the Si-LED works at high forward current, the output optical power increases rapidly with the increase of forward current, which is a non-linear growth similar to exponential. To the best of our knowledge, such a phenomenon has never been reported before. Moreover, when the forward current is at 200 mA, the optical power density reaches 32.7 nW·μm 2 , which is two or three orders higher than that of other ever reported forward-biased Si-LED fabricated by standard CMOS technology. In addition, the red shift of the main peak in the spectra of Si-LED was observed and analyzed, and also the light-emission mechanism of each peak in the spectra was given.

Improved Performance of CMOS Terahertz Detectors by Reducing MOSFET Parasitic Capacitance

The parasitic circuit elements significantly affect rectification performance of metal-oxide-semiconductor field-effect transistor devices. In this paper, we develop a gate-source parasitic capacitance reduction technique by shifting the source lightly doped drain region and analyze the effectiveness on the improved performance of complementary metal-oxide-semiconductor (CMOS) terahertz (THz) detectors. It is experimentally found that for a 0.65-THz integrated CMOS detector, the maximum improvement of voltage responsivity and noise-equivalent power can be 155% and 70%, respectively, by suppressing the gate-source parasitic capacitance. The device simulation further quantitatively evaluates the gate-source parasitic capacitance under different gate-source overlap areas in the novel fabricated transistor structure. It reveals that a smaller gate-source overlap area can result in a lower gate-source parasitic capacitance, which is more favorable for reducing input THz signal leakage and therefore for increasing the THz responsivity. The works open a wide range of possibilities for the ease of design and fabrication of the high-performance THz detectors in standard CMOS technology.

Application prospect of metal-oxide-semiconductor silicon light emitting devices in integrated circuits

Photonic interconnects have potentials to break increasingly severe energy efficiency and bandwidth density bottlenecks of electrical interconnect in scaled complementary metal oxide semiconductor (CMOS) integrated circuits, leading to the emergence of optoelectronic integrated circuits (OEICs) that utilize electronic and photonic devices together in a synergistic way to achieve better performance than those based on pure electronic device technology. By reviewing the progresses of Si-based light-emitting device, the schematic of MOS-like light source integrated with waveguides and the following photodetector is analyzed for its availability. It is believed that on-chip optical interconnects could be achieved by standard CMOS technology successfully with the speed as fast as the velocity of light, supplying propulsions for nest-generation OEICs.

A fully-integrated 16-channel EEG readout front-end for neural recording applications

In this paper, a power-efficient, low noise analog front-end (AFE) is presented which employs the chopper-stabilized technique. A new instrumentation amplifier structure leads to a high input impedance beyond 10 GΩ at the frequency of 10 Hz. Furthermore, an adaptive DC servo loop (DSL) is proposed which is conditionally activated to minimize the negative impact of this block on the noise performance of the AFE. The integrated input-referred noise of the amplifier is 1.33 µVrms and 1.19 µVrms over the 0.5 Hz–100 Hz frequency range when the DSL is enabled or disabled, respectively. Also, considering different aspects of the AFE, a new comprehensive figure of merit (FOM) is introduced to compare different state-of-the-art biopotential amplifiers. The power consumption and bandwidth of the designed 16-channel AFE are 15.81 µW and 235 Hz, respectively. The circuit is realized in the 180 nm standard complementary metal–oxide–semiconductor technology using a 1 V power supply.

Performance Optimization and Improvement of Silicon Avalanche Photodetectors in Standard CMOS Technology

This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs’ structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.

Analog Spike-Timing-Dependent Resistive Crossbar Design for Brain Inspired Computing

With the rapid advancement in the complementary metal-oxide-semiconductor (CMOS) technology, the performance of neuromorphic computing systems that employed the emerging devices has entered a new era of high accuracy and energy efficient operations. As one of the most fundamental components in computing systems, encoding scheme characterizes the relationship between the stimulus and the individual or ensemble neuronal responses. Although rate encoding is easier to implement and with high error tolerance, temporal encoding offers high data density and energy efficiency. In this paper, an inter-spike interval (ISI)-based resistive crossbar neuromorphic design, built with the standard CMOS technology, is proposed. Our proposed decoder exhibits not only computation accuracy but also robustness. Another worth-mentioning achievement is the data compressor in our work, which is based on the spike temporal encoding scheme. In this paper, design and performance analysis for proposed ISI-based resistive crossbar are elaborated; as well as the application of our proposed design. 24 patterns are adopted to encode the sensory information which are successfully represented by seven inter-spike intervals leading to significantly high compression rate. To evaluate the performance, a test bench of video frames consisting one person rotating her head from 0° to 75° with an increment of 15° has been employed. The results showed that the ISI code has better performance in both recognition rate and converging speed.

Thermal Resistance Model for Standard CMOS Thermoelectric Generator

In this paper, an accurate thermal resistance model for a micro-thermoelectric generator ( $\mu $ TEG) designed using standard complementary metal-oxide-semiconductor (CMOS) technology is presented. The optimal dimensions for the $\mu $ TEG are determined based on the new $\mu $ TEG thermal model. The presented models are verified with three-dimensional numerical simulations and compared to published experimental results and the presented models exhibited very good accuracy. An improved output power is obtained when using the new thermal resistance model to determine accurate optimal device dimensions. In this paper, a 1-cm2 cross sectional area $\mu $ TEG based on a $0.13~\mu \text{m}$ UMC standard CMOS technology is proposed. An output power of $9.25~\mu \text{W}$ is produced at 2.34 K of temperature difference between the hot and cold sides of the $\mu $ TEG. The introduced compact models for thermal resistance and the delivered power model are compatible with SPICE based simulators and hence can be integrated with circuit simulations.

Ultra‐low‐power, high PSRR CMOS voltage reference with negative feedback

Based on negative feedback technique, a complementary metal–oxide semiconductor (CMOS) voltage reference with ultra‐low‐power, low supply voltage and high‐power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from −20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only −113 dB at 1 Hz, −64 dB at 1 kHz, respectively.

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

A 10‐bit pipelined analogue‐to‐digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n‐well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge‐pump‐based concept that avoids the use of power‐area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field‐effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area‐power‐cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non‐linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non‐linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal‐to‐noise plus distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

Ultralow power, high fill factor smart complementary metal oxide semiconductor image sensor with motion detection capability

Bandwidth saving, power consumption, and fill factor improvement are known as vitally important challenges image sensor designers face in order to accomplish high-performance imaging systems. This paper presents an ultralow power, high fill factor smart complementary metal oxide semiconductor (CMOS) image sensor with motion detection capability. In this efficient methodology, the amount of redundant data processed in unimportant frames has been reduced significantly, and therefore, the proposed imaging system consumes less power compared with counterpart imagers. Furthermore, a pixel structure is introduced that outputs two consecutive frame voltages in series, with the result that the pixel size is minimized and a higher fill factor is achieved. In order to simulate the image capturing procedure, a state-of-the-art approach based on MATLAB and HSPICE software is devised, which is another important achievement of this paper. The performance of this technique is demonstrated using a 64×64 pixel sensor designed in a 0.18-μm standard CMOS technology. The sensor chip consumes 0.2 mW of power while operating at 100 fps with a fill factor of 45%.