Standard Complementary Metal Oxide Semiconductor Research Articles

Design and optimization of backside illuminated image sensor for epiretinal implants

Backside illuminated pixel structure is proposed and evaluated as the building block for the image sensor being used as epiretinal prosthesis implant. The image sensor pixel is designed with the parameters of 90nm technology node of standard CMOS (Complementary Metal Oxide Semiconductor) process. The image sensor is consisted of a p-sub/n-well structure as the photosensitive area with the pixel pitch of 20μm. The maximum fill factor is observed due to separation of photosensitive area with the readout transistor surface in backside illumination technology. 90% quantum efficiency at 600nm wavelength and the dark current of 74.6nA/cm2 at room temperature is achieved for the optimized pixel. The application of deep backside Deep Trench Isolation (DTI), with high depth n-well doping profiles, results in a significant reduction of crosstalk (5.6% total crosstalk).

Low‐jitter, high‐linearity current‐controlled complementary metal oxide semiconductor relaxation oscillator with optimised floating capacitors

A new complementary metal oxide semiconductor (CMOS) relaxation oscillator featuring with high linearity and low-jitter is presented in this study. The high linearity between the frequency and control current is achieved by adopting the floating capacitor and the independent charged and discharged loops. The low-jitter performance is gained because of that the voltage across the floating capacitor is larger than the conventional oscillator. The proposed circuit is compatible with standard CMOS process and one test-chip with typical frequency of 6.66 MHz was implemented in the 0.5 μm (bipolar–CMOS–double-diffused metaloxide semiconductor (DMOS)) (BCD) process. The measured results show that <0.86% non-linearity in the current–frequency transfer function from 1 to 6.66 MHz without trimming. The cycle-to-cycle jitter was <112 ppm.

Polarization-selective uncooled infrared sensor with asymmetric two-dimensional plasmonic absorber

A polarization-selective uncooled infrared (IR) sensor was developed based on an asymmetric two-dimensional plasmonic absorber (2-D PLA). The 2-D PLA has an Au-based 2-D periodic dimple structure, where photons can be manipulated by spoof surface plasmon polaritons. Asymmetry was introduced into the 2-D PLA to realize a polarization selective function. Numerical investigations demonstrate that a 2-D PLA with ellipsoidal dimples (2-D PLA-E) gives rise to polarization-dependent absorption properties due to the asymmetric dimple shape. A microelectromechanical systems-based uncooled IR sensor was fabricated using a 2-D PLA-E through complementary metal oxide semiconductor (CMOS) and micromachining techniques. The 2-D PLA-E was formed with an Au layer sputtered on a SiO2 layer with ellipsoidal holes. The dependence of the responsivity on the polarization indicates that the responsivity is selectively enhanced according to the polarization and the asymmetry of the ellipsoids. The results provide direct evidence that a polarization-selective uncooled IR sensor can be realized simply by the introduction of asymmetry to the surface structure of the 2-D PLA, without the need for a polarizer or optical resonant structures. In addition, a pixel array where each pixel has a different detection polarization could be developed for polarimetric imaging using standard CMOS and micromachining techniques.

On‐Chip Manipulation of Magnetic Beads for Integrated Immunosensor

SUMMARYThe purpose of this work is in‐plane manipulation of dispersed magnetic beads on a chip. This makes an immunoassay chip that completes all its procedures on itself and eliminates any off‐chip components. A test chip was drawn in a 180 nm standard complementary metal oxide semiconductor process and tested. Beads with a diameter of 2.8 μm were diluted and applied to the chip. The chip successfully manipulated them with an affordable current down to 5 mA.

Bioinspired Focal-Plane Polarization Image Sensor Design: From Application to Implementation

In this paper, a bioinspired monolithic complementary metal-oxide-semiconductor (CMOS) polarization image sensor is described as a solution to real-time polarization image capture. Metallic wire-grid gratings are integrated onto standard CMOS image sensor arrays with different orientations. A numerical analysis is performed to guide the design of the wire-grid arrays. Experimental results from different CMOS processing units are compared. A current-mode polarization processing unit is designed, fabricated, and tested in order to perform the extraction of the polarization characteristics from the captured intensities. This paper illustrates how polarization image processing can be used to monitor live cells. Several polarization processing methods with different computational complexity and data requirements have been applied and compared.

Improved performance and low cost OLED microdisplay with titanium nitride anode

This work experimented on the TEOLED (Top-emitting Organic Light-Emitting Diode) using the TiN (titanium nitride) as the anode for the microdisplays based on the CMOS (Complementary Metal–Oxide–Semiconductor) integrated circuit substrate. TiN is a hard, dense, and refractory material with steady physical and chemical characteristics. It is proved in this work to be a good candidate for the anode of the TEOLED due to its good electrical and optical characteristics. A SXGA resolution OLED microdisplay is designed and developed with TiN anodes. The luminance reaches beyond 2700cd/m2 when the operating voltage is below 5V. The power efficiency reaches 13lm/W at the luminance of 1000cd/m2. As a conclusion, TiN can be used to solve the incompatibility problem between the CMOS process and the OLED process. By fabricating the top metal coated with TiN as the TEOLED anodes in the standard CMOS process, it is not necessary to build a new separate post-process line for the anodes in the mass manufacture. Hence, the process step for the CMOS-based OLED microdisplay will be simplified, huge cost will be saved and the production yield will also be improved.

High-performance subwavelength grating coupler based on high-reflectivity grating reflector

A high-performance and compact binary blazed subwavelength grating coupler was designed, which consists of the upper grating coupler and the lower layer grating reflector. A large part of light transmitted out to the substrate due to the existence of gratings can be efficiently reflected with normal incidence. Then, the propagating light is augmented and the coupling efficiency obtains its maximum value. By the appropriate choice of grating parameters, including thicknesses, periods, height, and filling factor, a coupling efficiency of beyond 80% at wavelengths from 1.535 to 1.555 μ m is calculated. Finally, the device layout is simple, feasible, and compatible with standard complementary metal-oxide semiconductor technology processing.

Scaling computation with silicon photonics

Abstract

Ion traps fabricated in a CMOS foundry

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Electric field manipulation of nonvolatile magnetization in Au/NiO/Pt heterostructure with resistive switching effect

The electrical field manipulation of magnetization is investigated in an Au/NiO/Pt heterostructure, which is fully compatible with the standard complementary metal-oxide semiconductor process. Reversible and stable unipolar resistive switching effects as well as a significant nonvolatile change of the magnetization are observed in this device during the set and reset processes at room temperature. Further analysis indicates that the formation and rupture of metallic Ni conducting filaments caused by the electric field would be responsible for the changes of resistivity and magnetization. The coexistence of the electric field control of magnetization change and resistive switching makes Au/NiO/Pt heterostructure a promising candidate for the multifunctional memory devices.

Quasi‐digital front‐ends for current measurement in integrated circuits with giant magnetoresistance technology

In this study, the authors report on two different electronic interfaces for low-power integrated circuits electric current monitoring through current-to-frequency ( I-f ) conversion schemes. This proposal displays the intrinsic advantages of the quasi-digital systems regarding direct interfacing and self-calibrating capabilities. In addition, as current-sensing devices, they have made use of the giant magnetoresistance (GMR) technology because of its high sensitivity and compatibility with standard complementary metal oxide semiconductor processes. Single elements and Wheatstone bridges based on spin-valves and magnetic tunnel junctions have been considered. In this sense, schematic-level simulations for integration in Austria Microsystems 0.35 μm technology have been corroborated by means of experimental measurements with the help of printed circuit board prototypes and real GMR devices. Tables with relevant parameters (silicon area, power consumption, sensitivity etc.) have been constructed as practical tools for designers. Electric currents down to 2 μA have been resolved in this way.

Spin nano-oscillator-based wireless communication.

Spin–torque nano–oscillators (STNOs) have outstanding advantages of a high degree of compactness, high–frequency tunability, and good compatibility with the standard complementary metal–oxide–semiconductor process, which offer prospects for future wireless communication. There have as yet been no reports on wireless communication using STNOs, since the STNOs also have notable disadvantages such as lower output power and poorer spectral purity in comparison with those of LC voltage–controlled oscillators. Here we show that wireless communication is achieved by a proper choice of modulation scheme despite these drawbacks of STNOs. By adopting direct binary amplitude shift keying modulation and non–coherent demodulation, we demonstrate STNO–based wireless communication with 200–kbps data rate at a distance of 1 m between transmitter and receiver. It is shown, from the analysis of STNO noise, that the maximum data rate can be extended up to 1.48 Gbps with 1–ns turn–on time. For the fabricated STNO, the maximum data rate is 5 Mbps which is limited by the rise time measured in the total system. The result will provide a viable route to real microwave application of STNOs.

Nanomechanical switches based on metal-insulator-metal capacitors from a standard complementary-metal-oxide semiconductor technology

We report experimental demonstrations of contact-mode nano-electromechanical switches obtained using a capacitor module based on metal-insulator-metal configuration of a standard commercial complementary metal oxide semiconductor technology. The developed 2 terminals Titanium Nitride switches operate at low voltages (∼10 V) thanks to its small gap (27 nm), showing an excellent ION/IOFF ratio (104) and abrupt behavior (5 mV/decade, one decade of current change is achieved with a 5 mV voltage variation). A switch configuration is also presented where using two electrodes three different contact mode states can be obtained, adding functionalities to mechanical switches configurations.

A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

A 0.5---2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5---2.5 GHz band. The noise figure (NF) is 3.9---5.0 dB and the IIP3 is 3.1---3.6 dBm. The power consumption is only 910 uW.

Balanced Gm‐C filters with improved linearity and power efficiency

SummaryA novel Gm‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential Gm‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole Gm‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth Gm‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Design of Fully Integrated Impedimetric CMOS Biosensor for DNA Detection

This paper described a label-free and fully integrated impedimetric biosensor using standard Complementary Metal Oxide Semiconductor (CMOS) technology to measure both capacitance and resistance of the electrode-electrolyte interface. Conventional impedance biosensors usually use bulky and expensive instruments to monitor the impedance change. This paper demonstrates a low power, high gain and low cost impedance readout circuit design for detecting the biomolecular interactions of deoxyribonucleic acid (DNA) strands at the electrode surface. The proposed biosensor circuit is composed of a transimpedance amplifier (TIA) with two quadrature phase mixers and finally integrated with 5μm x 5μm microelectrode based on 0.18μm Silterra CMOS technology process with 1.8V supply. The output value of the readout circuit is used to estimate the amplitude and phase of the measured admittance. The developed TIA can achieve a gain of 88.6dB up to a frequency of 50MHz. It also has very good linearity up to 2.7mA and the overall dynamic range is approximately 90dB.

Block-Based Low-Power CMOS Image Sensor with a Simple Pixel Structure

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 <TEX>${\mu}m$</TEX> process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

A Low-Voltage and Label-Free Impedance-Based Miniaturized CMOS Biosensor for DNA Detection

This study designs a low-voltage, label-free and fully integrated impedance-based biosensor using standard complementary metal oxide semiconductor (CMOS) technology to compute both capacitance and resistance of the electrode-electrolyte interface. The proposed biosensor circuit is composed of a common-gate transimpedance amplifier (CG-TIA) with two quadrature phase Gilbert cell double-balanced mixers and finally integrated with microelectrode using 0.18 µm Silterra CMOS technology process. The output value of the readout circuit was used to estimate the magnitude and phase of the measured admittance. The developed CG-TIA can achieve a gain of 88.6 dB up to a frequency of 50 MHz. The overall dynamic range was approximately 116 dB.

Cost-Effective Schottky-Barrier Diode Array With Ni–Silicidation Accessing Low Power Phase-Change Memory

A cost-effective fabrication of Schottky-barrier (SB) diode steering element for low power phase-change memory (PCM) application is realized. While superior drivability in conventional PN diode array, SB diode array with 0.0193- μm2 (5F2), performing higher switching speed, sufficient drive current density of ~ 26.30 mA/μm2, disturbance immunity, and lower power consumption has been manufactured under 40-nm standard complementary metal oxide semiconductor technology. Simultaneously, different performance specifications, including integration scheme, JON/JOFF ratio, temperature characteristics, and scalability have been studied in detail and compared in two categories of accessing diode arrays. It manifests that the scaled SB diode array is suitable for full operation of PCM.

High temperature behavior of multi-region direct current current–voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal–oxide–semiconductor field-effect-transistors reliability

With the process compatibility with the mainstream standard complementary metal–oxide–semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular for its better tradeoff between breakdown voltage and performance, especially for smart power applications. A multi-region direct current current–voltage (MR-DCIV) technique with spectroscopic features was demonstrated to map the interface state generation in the channel, accumulation and STI drift regions. High temperature behavior of MR-DCIV spectroscopy was analyzed and a physical model was verified. Degradation of STI-based LDMOS transistors under high temperature reverse bias (HTRB) stress is experimentally studied by MR-DCIV spectroscopy. The impact of interface state location on device electrical characteristics was investigated. Our results show that the major contribution to HTRB degradation, in term of the on-resistance degradation, was attributed to interface state generation under STI drift region.