Standard Processor Research Articles

Nonlinear Visual Control of Unmanned Aerial Vehicles in GPS-Denied Environments

In this paper, we propose a nonlinear controller that stabilizes unmanned aerial vehicles in GPS-denied environments with respect to visual targets by using only onboard sensing. The translational velocity of the vehicle is estimated online with a nonlinear observer, which exploits spherical visual features as the main source of information. With the proposed solution, only four visual features have shown to be enough for the observer to operate in a real scenario. In addition, the observer is computationally light with constant numerical complexity, involving small-dimension matrices. The observer output is then exploited in a nonlinear controller designed with an integral backstepping approach, thus yielding a novel robust control system. By means of Lyapunov analysis, the stability of the closed-loop system is proved. Extensive simulation and experimental tests with a quadrotor are carried out to verify the validity and robustness of the proposed approach. The control system runs fully onboard on a standard processor, and only a low-cost sensing suite is employed. Tracking of a target whose speed exceeds 2 $\mathrm{m/s}$ is also considered in the real-hardware experiments.

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation

In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault analysis (DFA), such as redundancy calculation, masked and–or, and wave dynamic differential logic. The proposed countermeasure can thwart both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li’s countermeasure concept that removes the dependency between FSs and secret data. The postmanufacture configuration of the CDBs allows minimization of the overhead in operating frequency that comes from manufacture variability. In this paper, we also present an implementation of the proposed countermeasure in application-specified integrated circuit, and describe its configuration method. We then investigate the hardware overhead of the proposed countermeasure for an advanced encryption standard processor and demonstrate its validity through an experiment.

Libcloudph++ 1.0: a single-moment bulk, double-moment bulk, and particle-based warm-rain microphysics library in C++

Abstract. This paper introduces a library of algorithms for representing cloud microphysics in numerical models. The library is written in C++, hence the name libcloudph++. In the current release, the library covers three warm-rain schemes: the single- and double-moment bulk schemes, and the particle-based scheme with Monte Carlo coalescence. The three schemes are intended for modelling frameworks of different dimensionalities and complexities ranging from parcel models to multi-dimensional cloud-resolving (e.g. large-eddy) simulations. A two-dimensional (2-D) prescribed-flow framework is used in the paper to illustrate the library features. The libcloudph++ and all its mandatory dependencies are free and open-source software. The Boost.units library is used for zero-overhead dimensional analysis of the code at compile time. The particle-based scheme is implemented using the Thrust library that allows one to leverage the power of graphics processing units (GPU), retaining the possibility of compiling the unchanged code for execution on single or multiple standard processors (CPUs). The paper includes a complete description of the programming interface (API) of the library and a performance analysis including comparison of GPU and CPU set-ups.

FPGA Implementation of a Simple 3D Graphics Pipeline

Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation) and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing).

Exploring the performance–power–energy balance of low-power multicore and manycore architectures for anomaly detection in remote sensing

In this paper, we perform an experimental study of the interactions between execution time (i.e., performance), power, and energy that occur in modern low-power architectures when executing the RX algorithm for detecting anomalies in hyperspectral images (i.e., signatures which are spectrally different from their surrounding data). We believe this is important because, for airborne and spaceborne remote sensing missions, power and/or energy can be in practice as relevant as performance. In this sense, this paper investigates whether several recent low-power multithreaded architectures, from ARM and NVIDIA, can be a practical alternative in this domain to a standard high-performance multicore processor, using the RX anomaly detector as a case study.

An Assessment of ScanSAR Interferometric Processing Using Full-Aperture Approach

Scanning synthetic aperture radar (ScanSAR) interferometry using full-aperture approach has been used in the geophysical community when a standard ScanSAR interferometric processor is not available. Although interferograms can routinely be produced as well, some concerns about the full-aperture processing still remain. In this letter, we assess the quality of the interferogram produced by this approach. After theoretical analyses, we compare interferograms produced by the full-aperture approach and the standard burst-by-burst approach. Comparison results show that the difference between the final interferograms produced by the two approaches is small. For the data processed, the mean value and standard deviation of the difference phase are 8.36 ×10-4 rad and 3.60 ×10-1 rad, respectively. These results confirm the availability of full-aperture processing for most of the geophysical applications using ScanSAR interferometry.

Advantages of GPU technology in DFT calculations of intercalated graphene

Over the past few years, the expansion of general-purpose graphic-processing unit (GPGPU) technology has had a great impact on computational science. GPGPU is the utilization of a graphics-processing unit (GPU) to perform calculations in applications usually handled by the central processing unit (CPU). Use of GPGPUs as a way to increase computational power in the material sciences has significantly decreased computational costs in already highly demanding calculations. A level of the acceleration and parallelization depends on the problem itself. Some problems can benefit from GPU acceleration and parallelization, such as the finite-difference time-domain algorithm (FTDT) and density-functional theory (DFT), while others cannot take advantage of these modern technologies. A number of GPU-supported applications had emerged in the past several years (www.nvidia.com/object/gpu-applications.html). Quantum Espresso (QE) is reported as an integrated suite of open source computer codes for electronic-structure calculations and materials modeling at the nano-scale. It is based on DFT, the use of a plane-waves basis and a pseudopotential approach. Since the QE 5.0 version, it has been implemented as a plug-in component for standard QE packages that allows exploiting the capabilities of Nvidia GPU graphic cards (www.qe-forge.org/gf/proj). In this study, we have examined the impact of the usage of GPU acceleration and parallelization on the numerical performance of DFT calculations. Graphene has been attracting attention worldwide and has already shown some remarkable properties. We have studied an intercalated graphene, using the QE package PHonon, which employs GPU. The term ‘intercalation’ refers to a process whereby foreign adatoms are inserted onto a graphene lattice. In addition, by intercalating different atoms between graphene layers, it is possible to tune their physical properties. Our experiments have shown there are benefits from using GPUs, and we reached an acceleration of several times compared to standard CPU calculations.

The Feynman tools for quantum information processing: Design and implementation

The Feynman tools for quantum information processing: Design and implementation

TOPS-Mode Raw Data Processing Using Chirp Scaling Algorithm

This paper presents four imaging approaches for terrain observation by progressive scans (TOPS)-mode SAR focusing, all of which take advantage of modified chirp scaling (CS) algorithms according to echo properties in TOPS. After adopting different azimuth preprocessing steps to resolve the aliased Doppler spectra, the resulting TOPS raw data can be handled by a classic CS processor. Unfortunately, the resulting images would appear back folding, if only a standard stripmap processor is adopted. To avoid or resolve azimuth back folding in the final focused TOPS SAR images, four modified CS algorithms are presented according to special properties of the slow time-frequency diagram in TOPS. Imaging results on point targets validate the presented imaging approaches.

Synthesizable Manycore Processor Designs with FPGA in Teaching Computer Architecture

Manycore processor architectures are currently very widely used in almost all computer systems. Furthermore, many computer science department have started to teach parallel programming on manycore system platforms. To best understand the parallel programming on those manycore processors, the classes on manycore processor architecture also have to be provided. However, most current undergraduate computer architecture classes have not yet provided. In this paper, we have design a manycore processor design using a conventional MIPS processor design that is considered as a standard processor architecture model in a traditional undergraduate computer architecture class. Synthesize manycore processor models are developed in 850 lines of Verilog-HDL together with simple parallel applications so students can understand the entire manycore processor design and can learn the basics of the manycore system including underlying communication architecture.

CudaMap: a GPU accelerated program for gene expression connectivity mapping

BackgroundModern cancer research often involves large datasets and the use of sophisticated statistical techniques. Together these add a heavy computational load to the analysis, which is often coupled with issues surrounding data accessibility. Connectivity mapping is an advanced bioinformatic and computational technique dedicated to therapeutics discovery and drug re-purposing around differential gene expression analysis. On a normal desktop PC, it is common for the connectivity mapping task with a single gene signature to take > 2h to complete using sscMap, a popular Java application that runs on standard CPUs (Central Processing Units). Here, we describe new software, cudaMap, which has been implemented using CUDA C/C++ to harness the computational power of NVIDIA GPUs (Graphics Processing Units) to greatly reduce processing times for connectivity mapping.ResultscudaMap can identify candidate therapeutics from the same signature in just over thirty seconds when using an NVIDIA Tesla C2050 GPU. Results from the analysis of multiple gene signatures, which would previously have taken several days, can now be obtained in as little as 10 minutes, greatly facilitating candidate therapeutics discovery with high throughput. We are able to demonstrate dramatic speed differentials between GPU assisted performance and CPU executions as the computational load increases for high accuracy evaluation of statistical significance.ConclusionEmerging ‘omics’ technologies are constantly increasing the volume of data and information to be processed in all areas of biomedical research. Embracing the multicore functionality of GPUs represents a major avenue of local accelerated computing. cudaMap will make a strong contribution in the discovery of candidate therapeutics by enabling speedy execution of heavy duty connectivity mapping tasks, which are increasingly required in modern cancer research. cudaMap is open source and can be freely downloaded from http://purl.oclc.org/NET/cudaMap.

Research on the Characteristics of Steel Frame Node under Explosive and Impact Load

With the characteristics of huge energy,short acting time and large destructiveness, Explosive and Impact Load leads a large punching force towards construction units. Once happened, it can cause serious of damaging effects. Therefore,the explosion protection performance of construction is being more and more concerned[1].The large finite element analysis software ABAQUS is being used to deal with numerical simulation of cross steel frame node, to analyses the response of the steel frame node and to discusses different steel material parameters on the influence of the nodes dynamic response under the effect of Explosive and Impact Load in this paper. According to conclusions, increase strength and modulus of elasticity of steel can reduce the damage of Explosive and Impact Load to construction. Meanwhile taking advantage of the function of transferring information between explicit processor and standard processor in ABAQUS, this paper analyses the effect of Explosive and Impact Load on steel frame node under low cyclic loading and concludes that it is harmful to the structural performance that the effect of Explosive and Impact Load can lower the ductility of the structure. According to the conclusion from the research on steel frame nodes characteristics under the effect of Explosive and Impact Load, this paper present that negative influence of Explosive and Impact Load should be taken fully into account, beneficial materials to explosion protection performance should be choosen and the corresponding measures to improve the ductility of structure should be taken to reduce structures degree of damage under Explosive and Impact Load in future structural design. All the research have a certain significance to the future structural design of explosion protection.

A New Imaging Approach for Burst Mode Synthetic Aperture Radar

Burst imaging schemes such as ScanSAR and Terrain Observation by Progressive Scans (TOPS) are often adopted to obtain wide swath coverage by synthetic aperture radar (SAR) systems with electronic beam steering in elevation. Long burst trains with zero padding in the inter-burst intervals can be focused by standard stripmap processors for the phase preserving product. However, this approach is less efficient due to the larger azimuth data extension. We discuss an efficient imaging approach for burst mode SAR. The key point of the proposed procedure is a postfiltering step after standard stripmap processors, which employs an azimuth convolution between the focused SAR data and the selected chirp signal. The postfiltering step is generalized by a two-step focusing technique formerly proposed for spotlight/sliding spotlight SAR. This approach extends the focusing capacity of standard stripmap processors to process burst mode raw data. Moreover, it is highly efficient, as it requires a very limited azimuth data extension.

Optimizing Parallel S n Sweeps on Unstructured Grids for Multi-Core Clusters

In particle transport simulations, radiation effects are often described by the discrete ordinates (Sn) form of Boltzmann equation. In each ordinate direction, the solution is computed by sweeping the radiation flux across the grid. Parallel Sn sweep on an unstructured grid can be explicitly modeled as topological traversal through an equivalent directed acyclic graph (DAG), which is a data-driven algorithm. Its traditional design using MPI model results in irregular communication of massive short messages which cannot be efficiently handled by MPI runtime. Meanwhile, in high-end HPC cluster systems, multicore has become the standard processor configuration of a single node. The traditional data-driven algorithm of Sn sweeps has not exploited potential advantages of multi-threading of multicore on shared memory. These advantages, however, as we shall demonstrate, could provide an elegant solution resolving problems in the previous MPI-only design. In this paper, we give a new design of data-driven parallel Sn sweeps using hybrid MPI and Pthread programming, namely Sweep-H, to exploit hierarchical parallelism of processes and threads. With special multi-threading techniques and vertex schedule policy, Sweep-H gets more efficient communication and better load balance. We further present an analytical performance model for Sweep-H to reveal why and when it is advantageous over former MPI counterpart. On a 64-node multicore cluster system with 12 cores per node, 768 cores in total, Sweep-H achieves nearly linear scalability for moderate problem sizes, and better absolute performance than the previous MPI algorithm on more than 16 nodes (by up to two times speedup on 64 nodes).

Review of stereo vision algorithms and their suitability for resource-limited systems

A significant amount of research in the field of stereo vision has been published in the past decade. Considerable progress has been made in improving accuracy of results as well as achieving real-time performance in obtaining those results. This work provides a comprehensive review of stereo vision algorithms with specific emphasis on real-time performance to identify those suitable for resource-limited systems. An attempt has been made to compile and present accuracy and runtime performance data for all stereo vision algorithms developed in the past decade. Algorithms are grouped into three categories: (1) those that have published results of real-time or near real-time performance on standard processors, (2) those that have real-time performance on specialized hardware (i.e. GPU, FPGA, DSP, ASIC), and (3) those that have not been shown to obtain near real-time performance. This review is intended to aid those seeking algorithms suitable for real-time implementation on resource-limited systems, and to encourage further research and development of the same by providing a snapshot of the status quo.

Comparison of Hybrid Sorting Algorithms Implemented on Different Parallel Hardware Platforms

Sorting is a common problem in computer science. There are lot of well-known sorting algorithms created for sequential execution on a single processor. Recently, hardware platforms enable to create wide parallel algorithms. We have standard processors consist of multiple cores and hardware accelerators like GPU. The graphic cards with their parallel architecture give new possibility to speed up many algorithms. In this paper we describe results of implementation of a few different sorting algorithms on GPU cards and multicore processors. Then hybrid algorithm will be presented which consists of parts executed on both platforms, standard CPU and GPU.

Data cache organization for accurate timing analysis

Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

Comment on “Long Island Sound Coastal Observatory: assessment of above-water radiometric measurement uncertainties using collocated multi and hyperspectral systems”

Harmel et al. [Appl. Opt.50, 5842 (2011)] presented an intercomparison of products from collocated above-water radiometric measurements performed with a Hyperspectral Surface Acquisition System (HyperSAS) and a multispectral Sea-viewing Wide Field of View Sensor Photometer Revision for Incident Surface Measurements (SeaPRISM). Radiometric products from HyperSAS data were determined with a processing code written by the authors, while products from SeaPRISM measurements were obtained with the standard processor of the Ocean Color component of the Aerosol Robotic Network (AERONET-OC). Despite the application of equivalent processing schemes, results exhibit spectrally averaged unbiased relative differences of +26% between HyperSAS and SeaPRISM exact normalized water leaving radiances, L(WN). Harmel et al. concluded that the sun-glint correction scheme applied for SeaPRISM data reduction is a major reason for the observed differences. This comment rejects the former conclusion as being supported by a wrong interpretation of the AERONET-OC processing scheme, and a consequent failure in describing the spectral properties of the glint radiance determined from SeaPRISM data. Afterward, the differences between HyperSAS and SeaPRISM L(WN) reported by Harmel et al. are challenged with intercomparison results from collocated measurements periodically performed over almost a decade with an in-water multispectral system and SeaPRISM. Results for L(WN) from the in-water system show spectrally averaged unbiased relative differences of +1% with respect to SeaPRISM values.

A practical approach to speech processor for auditory prosthesis using DSP and FPGA

Auditory prosthesis (AP) is a widely used electronic device for patients suffering with severe hearing loss by electrically stimulating the auditory nerve using an electrode array surgically placed inside the inner ear. The AP also known as cochlear implant (CI) mainly contains external Body worn Speech Processor (BWSP) and internal Implantable Receiver Stimulator (IRS). BWSP receives an external sound or speech and generates encoded speech data bits for transmission to IRS via Radio Frequency transcutaneous link for excitation of electrode array placed in the inner ear. Development of BWSP and IRS involves normally the use of either standard microprocessor or microcontroller or digital signal processor (DSP) or FPGA or ASIC devices. Sometimes the performance of the AP system using the standard processors cannot meet the requirement of the intended application. As the selected DSP processor (ADSP2185) from Analog Devices Inc. solely cannot perform the purpose of the speech processor for auditory prostheses, the Xilinx FPGA is added to fulfill the requirement. Combination of a standard processor such as DSP and FPGA may lead to the solution in both prototyping and target operational system. The ADSP2185 processor is used to realize the Continuous Interleaved Sampling (CIS) algorithm for speech signal processing and FPGA is used to realize the speech data encoding algorithm. This paper introduces practical implementations of digital speech processor for use in AP based on DSP ADSP-2185 and Xilinx's FPGA Spartan 3 with the description of practical data. The combination of ADSP2185 and FPGA is used to develop Speech Processor for an auditory prosthesis. FPGA implementation of speech data encoder is initially simulated using ModelSim and interfaced with ADSP2185. The entire embedded application is tested with real time speech signals by using laboratory model IRS and satisfactory results are observed.

Teaching cardiac electrophysiology modeling to undergraduate students: laboratory exercises and GPU programming for the study of arrhythmias and spiral wave dynamics

As part of a 3-wk intersession workshop funded by a National Science Foundation Expeditions in Computing award, 15 undergraduate students from the City University of New York(1) collaborated on a study aimed at characterizing the voltage dynamics and arrhythmogenic behavior of cardiac cells for a broad range of physiologically relevant conditions using an in silico model. The primary goal of the workshop was to cultivate student interest in computational modeling and analysis of complex systems by introducing them through lectures and laboratory activities to current research in cardiac modeling and by engaging them in a hands-on research experience. The success of the workshop lay in the exposure of the students to active researchers and experts in their fields, the use of hands-on activities to communicate important concepts, active engagement of the students in research, and explanations of the significance of results as the students generated them. The workshop content addressed how spiral waves of electrical activity are initiated in the heart and how different parameter values affect the dynamics of these reentrant waves. Spiral waves are clinically associated with tachycardia, when the waves remain stable, and with fibrillation, when the waves exhibit breakup. All in silico experiments were conducted by simulating a mathematical model of cardiac cells on graphics processing units instead of the standard central processing units of desktop computers. This approach decreased the run time for each simulation to almost real time, thereby allowing the students to quickly analyze and characterize the simulated arrhythmias. Results from these simulations, as well as some of the background and methodology taught during the workshop, is presented in this article along with the programming code and the explanations of simulation results in an effort to allow other teachers and students to perform their own demonstrations, simulations, and studies.