Standard Cell Placement Problem Research Articles

On solving partition driven standard cell placement problem using firefly-based metaheuristic approach

The standard-cell placement problem has drawn great attention in the VLSI CAD domain. Being an NP complete problem, a spacious range of heuristic approaches exist in the literature for expeditiously organising the circuit elements on a VLSI chip design. The advancement in the partitioning algorithms has made the recursive bisection-based placement more attractive. The paper presents a metaheuristic approach based on firefly algorithm for partition-driven global standard cell placement. The algorithm is tested against circuits from the MCNC and IBM benchmark circuits and gives promising results in comparison to meta genetic approach.

On solving partition driven standard cell placement problem using firefly-based metaheuristic approach

On solving partition driven standard cell placement problem using firefly-based metaheuristic approach

Parallel Simulated Annealing Algorithm for Standard Cell Placement in VLSI Design

Annealing (SA) is a stochastic based heuristic optimization technique based on physical process of metal crystallization. Optimization of Non-Deterministic polynomial hard (NP-hard) problems of non-trivial sizes is done using heuristic approach. Until now, simulated annealing (SA), genetic algorithm (GA) and Hopfield neural network (HNN) were individually used for solving the standard cell placement (SCP) problem. Simulated annealing established as a powerful SCP optimization tool, its drawback has always been its appetite for computational resources. In light of this, we are interested in the application of these parallel simulated annealing algorithms with respect to standard cell placement. Several generalized algorithms proposed for parallelizing simulated annealing, only a few have been applied to cell placement. Parallel moves has been the most popular strategy and in this paper we present a new implementation of this approach.

A Swarm Random Walk Based Method for the Standard Cell Placement Problem

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

On The Performance of the Gravitational Search Algorithm

Gravitational Search Algorithms (GSA) are heuristic optimization evolutionary algorithms based on Newton's law of universal gravitation and mass interactions. GSAs are among the most recently introduced techniques that are not yet heavily explored. An early work of the authors has successfully adapted this technique to the cell placement problem, and shown its efficiency in producing high quality solutions in reasonable time. We extend this work by fine tuning the algorithm parameters and transition functions towards better balance between exploration and exploitation. To assess its performance and robustness, we compare it with that of Genetic Algorithms (GA), using the standard cell placement problem as benchmark to evaluate the solution quality, and a set of artificial instances to evaluate the capability and possibility of finding an optimal solution. Experimental results show that the proposed approach is competitive in terms of success rate or likelihood of optimality and solution quality. And despite that it is computationally more expensive due to its hefty mathematical evaluations, it is more fruitful on the long run.

Artificial bee colony for the standard cell placement problem

Placement is an important step in the VLSI design process, of which standard cell placement SCP is a well-studied problem. The four 'pure' major algorithms for placement include simulated annealing, quadratic placement, min-cut placement, and force-directed placement. The four pure algorithms are inadequate for today's complex problems; hybrid methods are better able to solve the current SCP problem sizes. The objective of this paper is to present a swarm intelligence-based method for SCP. The method used to solve the SCP problem is the artificial bee colony ABC algorithm, in conjunction with hMetis, a partitioning package. Our artificial bee colony PLacer tool abcPL, has been tested on the PEKU benchmark suite. Results obtained show that ABC is a promising approach for solving the SCP problem.

An Analytical Placer for VLSI Standard Cell Placement

Placement is the process of determining the exact locations of circuit elements within a chip. It is a crucial step in very large scale integration (VLSI) physical design, because it affects routability, performance, and power consumption of a design. In this paper, we develop a new analytical placer to solve the VLSI standard cell placement problem. The placer consists of two phases, multilevel global placement (GP) and detailed cell placement (DP). In the stage of GP, during the clustering stage, we use a nonlinear programming technique and a best-choice clustering algorithm to take a global view of the whole netlist and placement information, and then use an iterative local refinement technique during the declustering stage to further distribute the cells and reduce the wirelength. In the stage of DP, we develop a fast legalization algorithm to make the solution by global placement legal and use a cell order polishing to improve the legal solution. The proposed algorithm is tested on the IBM standard cell benchmark circuits and Peko suites. Experimental results show that our placer obtains high-quality results in a reasonable running time.

A parallel branch-and-cut approach for detailed placement

We introduce a technique that utilizes distributing computing resources for the efficient optimization of a traditional physical design problem. Specifically, we present a detailed placement strategy designed to exploit distributed computing environments, where the additional computing resources are employed in parallel to improve the optimization time. A Mixed Integer Programming (MIP) model and branch-and-cut optimization strategy are employed to solve the standard cell placement problem. By exploiting the problem structure, our algorithm improves upon the solutions afforded by existing optimization algorithms. First, an efficient batch-branching technique can eliminate several integer decision variables during each step of the optimization procedure. This batch-branching scheme can be performed serially or in parallel. In addition, custom cutting-planes are shown to significantly reduce the run time for optimizations as they efficiently refine the feasible region in order to quickly produce integer solutions. Our serial branch-and-cut strategies allow for significant reductions in wirelength, relative to the state-of-the-art commercial software package CPLEX, assuming a fixed allotment of time. Furthermore, we show that distributed computing resources can be used to significantly reduce the time required to achieve reductions in wirelength.

Performance Enhancement of Standard Cell Placement Techniques using Memetic Algorithm

The growing complexity in the electronic hardware now necessitates in improving the performance of searching algorithms. Genetic algorithms do not guarantee global optimum solution to NP-Hard problems but are generally good at finding acceptable solution to problems. In complex combinatorial spaces, hybridization with other optimization techniques can greatly improve the efficiency of search. Memetic algorithm (MA) is an improvisation over genetic algorithms (GA) that combines global and local search by using evolutionary algorithms to perform exploration while the local search methods are used for exploitation. Here, exploitation is the process of visiting entirely new regions of a search space where the gain can also be high. This paper discusses the (MAs) as a solution to Standard Cell Placement (SCP) problem and procedures are laid down to strike a balance between genetic search and local search in MAs. A comparison of MA with the already established results for SCP using conventional and Hybrid techniques by the author depicts improvement in the performance of SCP algorithm in terms of solution quality and computing speed. About 15% improvement in overall wire-length was observed along side it being 25% faster over the Tabu Search (TS) algorithm discussed in previous works of the author. General Terms: Algorithm, exploration, exploitation

Adaptive parameter control of evolutionary algorithms to improve quality-time trade-off

Parameter control of evolutionary algorithms (EAs) poses special challenges as EA uses a population and requires many parameters to be controlled for an effective search. Quality improvement is dependent on several factors, such as, fitness estimation, population diversity and convergence rate. A widely practiced approach to identify a good set of parameters for a particular class of problem is through experimentation. Ideally, the parameter selection should depend on the resource availability, and thus, a rigid choice may not be suitable. In this work, we propose an automated framework for parameter selection, which can adapt according to the constraints specified. To condition the parameter choice through resource constraint/utilization, we consider two typical scenarios, one where maximum available run-time is pre-specified and the other in which a utility function modeling the quality-time trade-off is used instead of a rigid deadline. We present static and dynamic parameter selection strategies based on a probabilistic profiling method. Experiments performed with traveling salesman problem (TSP) and standard cell placement problem show that an informed adaptive parameter control mechanism can yield better results than a static selection.

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction

Broadcast-based test compression techniques can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. In this paper, we first conduct a quantitative analysis that shows the simple broadcast architecture that cannot achieve good test time/data compression even under a test set with very high level of don't care bits. A multi-mode-segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast and serial. As a result, improved test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing length of the scan chains are also taken into account in the ordering process.

Force-Directed Methods for Generic Placement

This paper describes the implementation of a wire length-driven force-directed placer named FDP for generic placement. Specifically, it describes efficient force computation for cell spreading, numerical instabilities during force-directed placement, a means to avoid instabilities, and metrics for proper assessment of cell distribution throughout the placement region. It demonstrates that one of the greatest impediments to achieving high-quality placements using a force-directed placer lies in the large amount of cell overlap present in initial placements. This overlap makes the determination of cell ordering difficult and can lead to the inadvertent separation of highly connected cells. It is shown that median improvement and multilevel clustering improve cell ordering and aid in wire length minimization. Numerical results are presented for both standard cell and mixed-size placement problems. For standard cell problems, the tool generates placements that are, on average, 3% better than Capo9.0, but 5% worse than FengShui2.6. For mixed-size problems, FDP generated placements that are, on average, 2%-5% better than Capo9.0 and -5%--2% better than Fengshui2.6, depending on the presence (or absence) of pin offsets. Run times for FDP are higher than both Capo9.0 and FengShu2.6, although reasonable

An efficient quadratic placement based on search space traversing technology

A very large-scale standard cell placement problem has too complicated solution space for conventional analytical quadratic placement methods to achieve the “optimal” or near-optimal solution in it. The rugged terrain of solution space makes those methods easy to get stuck at local optima. In this paper, a novel quadratic placement based on search space traversing technology is proposed to search the optimal or near-optimal solution. This method first employs a pre-partitioning to cut down the problem scale and reconstruct the problem structure, and then combines the Lagrange relaxation method and the Lagrange multipliers method together in quadratic placement to solve the global placement. Finally, after eliminating overlaps, a full-chip force-directed post-adjustment is employed to reduce the negative effect of pre-partitioning. Experimental results on benchmarks show encouraging results.

Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering

Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem.

Optimization of placement by candidate sieving

A new algorithm for standard cell placement problem is presented. It is based on an idea that appropriate step by step reduction of allocatable cells for each component yields a good placement result. This algorithm named candidate sieving is applicable for discrete quadratic assignment problem with some constraint. The results obtained by candidate sieving are compared in terms of wire length and computing time with those obtained by simulated annealing which is considered the most popular method today. In many cases, candidate sieving has yielded shorter wire lengths, which are equal or almost equal to those obtained by simulated annealing, but with much less computing time.

INTERCONNECTION WIRE-LENGTH ESTIMATION IN VLSI STANDARD CELL PLACEMENT VIA NEURAL NETWORK

Neural Network is used as a tool for estimating interconnection wire-length in VLSI standard cell placement problem. Conventional methods for estimating the interconnection wire-length viz., Bounding Rectangle method, provide inaccurate estimate of the interconnection wire-length and does not depict the interconnection procedure in a layout and separates routing and placement tasks distinctly. The proposed mechanism utilizes the neural network characteristics in understanding the functional mapping between input and output, to estimate the interconnection wire-length. Experiments were performed for different number of cells with varying complexity of interconnections. In all the cases, the performance of the Neural Network is found to be superior to the results obtained using Bounding Rectangle procedure.

Use of a System of Recurrent Neural Networks for Solving the Cell Placement Problem in VLSI Design

Cell placement in VLSI design is an NP-complete problem. In this paper, we have tried to solve the standard cell placement problem using the Hopfield neural network model. Furthermore, a new system of coupled recurrent neural networks, which was designed to eliminate the drawbacks of the Hopfield neural network, is introduced. The performance of Hopfield networks with discrete and graded neurons is also investigated. The energy function corresponding to the chosen representation is given and the weight matrix and the inputs needed for the network are also computed in this work. Several different combinations of parameters were examined to find the optimum set of parameters which results in better and faster convergence. To show the effectiveness of our methods, cell placement problems up to 30 cells are considered and the results are compared with the results obtained by a genetic algorithm. Our results show that a system of coupled neural networks could be an efficient way to overcome the limitation of recurrent neural networks which consider only bilinear forms of the energy function.

Combinatorial optimization by stochastic evolution

A novel technique is introduced, called stochastic evolution (SE), for solving a wide range of combinatorial optimization problems. It is shown that SE can be specifically tailored to solve the network bisection, traveling salesman, and standard cell placement problems. Experimental results for these problems show that SE can produce better quality solutions than sophisticated simulated annealing (SA)-based heuristics in a much shorter computation time. >

An efficient heuristic for standard-cell placement

A new method is presented for optimization of the one and two-dimensional quadratic assignment problem. The method is suitable for placement problems as they appear in sea-of-gates and standard-cell layout styles for VLSI design. The method is based on recursive partitioning and is a generalization of the method introduced by Kuh et al. It is more flexible than Kuh's method because it does not require a special distribution of the external connections on the boundary of the chip. The time complexity of the algorithm is O( n Iog 2 n). A numerical evaluation of the method is presented, which shows its efficiency for generating near optimal solutions for the quadratic assignment problem as well as for practical standard-cell placement problems.