Staircase Modulation Research Articles

Optimum number of cascade cells for multilevel inverter considering redundancy strategies based on cost and reliability optimization

AbstractThis paper proposes an economical reliability‐oriented solution to determine the optimal number of cascade cells and redundancies for STATCOM using a Non‐Dominated Sorting Genetic (NSGA‐II) algorithm based on different redundancy configuration schemes. A multi‐objective optimization framework is presented, to minimize the total cost and maximize its reliability index by considering power quality issues. In the presented model, a new cost modelling is introduced considering the cost of inductor loss. The multilevel cascade topology with staircase modulation strategy is also taken into account. The effectiveness of the proposed optimization framework is validated by the NSGA‐II algorithm compared to the results of goal attainment and goal programming as decomposition single‐objective optimization methods. The results verify that the proposed multi‐objective optimization framework could be useful in the optimal selection of high‐voltage STATCOM levels in the presence of redundancies while ensuring the required level of reliability at the minimum cost. Also, the presented NSGA‐II optimization algorithm is applicable to maintain both objective functions at an acceptable value.

Analytical Approach to THD Formulation and Optimization in Sine-PWM-Based Single-Phase Multilevel Inverters With Variable DC Ratios

Asymmetric Multilevel Inverters (MLI) with Unequal Voltage Steps (UVS) are often combined with the Staircase Modulation (SCM) technique to improve both voltage and current THD - an approach known as Optimal Minimization of THD (OMTHD). This is usually achieved by varying both the Switching Angles (SA) and the DC source Ratios (DCR), to obtain the desired Modulation Index (MI) while THD is minimized. In this article, a novel Sine-PWM (SPWM) based OMTHD is considered as an alternative to SCM-based OMTHD. Because only the DCRs need to be optimized instead of both SAs and DCRs, the OMTHD process is simplified, while voltage THD, current THD, as well as power efficiency, are improved, especially for the medium-low MI range, compared to conventional SPWM. An analytical formulation of phase-voltage THD for UVS-based SPWM MLIs is derived and utilized for the novel SPWM-based OMTHD. Validation is carried out by theoretical analysis, digital simulations, and real-time C-HIL-based experiments.

An improved modulation method for modular multilevel converters based on particle swarm optimization

Modular multilevel converter (MMC) is the first topology choice for flexible DC transmission systems. This paper presents a particle swarm optimization (PSO) algorithm aided modulation method to calculate the improved selective harmonic elimination pulse width modulation (iSHE-PWM) switching angles with the aim of reducing the total harmonic distortion (THD) and output voltage error of MMC. The SHE-PWM has more controllable variables compared with the staircase modulation so that it can be used to improve the output current waveform quality. This method retains the advantages of easy to control and low frequency from the staircase modulation. But amplitude of its high-order harmonic is high and this paper improves it. Firstly the mathematical model of MMC is set up and corresponding expressions of THD and voltage error are given. The joint function of THD and voltage error is considered as the fitness function. The PSO algorithm was used to minimize the joint function for solving the optimal switching angles. Finally the proposed method is verified through simulation results showing its potential to successfully solve the problem of difficulty in obtaining the iSHE-PWM switching angles while minimizing the THD and output voltage error of the MMC.

Current-THD minimization in multilevel inverters with variable DC ratios utilizing a generic closed-form analytic formulation of line-voltage WTHD

This article presents a generic approach to load-current THD minimization in hard-switched Staircase Modulation (SCM) based three-phase (3ɸ) Multilevel Inverters (MLI) with either fixed or variable DC source Ratios (DCR). First, a computer-aided closed-form analytical formulation of Weighted THD (WTHD) applied directly to line-voltage waveforms is derived using Maple software and then verified against numerically-obtained results of previous works. The proposed symbolic analysis of Weighted Line-voltage THD (WLTHD) applies to 3ɸ-MLIs of any topology with Equal Voltage Steps (EVS) or Unequal Voltage Steps (UVS), and any number of voltage levels count (N), either odd or even. Such an analytical approach eliminates the risk of underestimation errors associated with numerical methods. The proposed closed-form WLTHD expression is then utilized for optimal minimization of current-THD in 3ɸ inductive loads with unconnected neutral. This is achieved by introducing a generic UVS-based Optimal Minimization of WLTHD (OMWLTHD), which calculates the optimum Phase Switching Angles (PSA) and the supply DC-Ratios (DCR), given any desired Modulation Index (MI), thus ensuring minimum current-THD across the entire linear MI range. The revealed OMWLTHD approach is fully validated by both digital simulations and controller plus hardware-in-loop (C-HIL) based experiments, using 7-, 8-, and even 13-level 3ɸ-MLIs of both EVS and UVS configurations. Furthermore, to reveal the impact of WLTHD minimization on actual load current-THD, the MLIs were loaded by a Resistive-Inductive-EMF (RLE) load, as well as a 3ɸ squirrel cage induction motor, thus representing a wide range of possible loads, such as motors and ac grids. The conclusive verification results have shown that in the case of 3-wire inductive loads with a power factor up to 0.95, the proposed UVS-based WLTHD optimization is more beneficial for current-THD minimization over other harmonic distortion quantifying parameters, as WLTHD presents the strongest correlation to actual load current THD when tested against any other parameter such as phase and line THD or WTHD. The revealed improvement in current THD was even more pronounced for UVS-based SCM compared to traditional EVS-based SCM. Additionally, MATLAB and Maple source files of the proposed WLTHD formulations and Excel-based pre-calculated optimum PSA and DCR sets for different values of N are provided as downloadable links to further enhance the contribution of the article.

Development of an Enhanced Selective Harmonic Elimination for a Single-Phase Multilevel Inverter with Staircase Modulation

A low device switching frequency is recommended for the operation of multilevel inverters (MLIs) to achieve reduced switching losses. Selective harmonic elimination (SHE) and total harmonic distortion (THD) minimization are the two primary switching angle estimation methodologies for low-frequency modulation control. In this regard, a new generalized condition has been developed in this paper for the SHE technique. This original condition will give an output voltage with improved THD in comparison to the conventional SHE technique, while achieving its primary objective of eliminating the specific harmonic content from the output voltage. The proposed condition has been formulated by estimating the error associated with the staircase waveform and the desired sinusoidal output at the fundamental frequency. An infinite harmonic count has been considered for the evaluation of the quality of output, to obtain an accurate THD value without any underestimation. The proposed technique is analyzed, and its critical features are studied in Simulink. The effectiveness of the present work has been also validated by the experimental results.

Design and implementation of a novel 35-level inverter topology with reduced switch count

• A novel 35-level multilevel inverter is designed with reduced switch count. • Experimental investigation is carried out with dynamic load changes. • Performance of the proposed inverter is evaluated with various parameters. • The proposed inverter is cost-effective with lower total standing voltage. • The proposed inverter has reduced power losses with improved efficiency of 93.37%. This paper projects a novel topology for the 35-level MLI. The proposed topology aims to generate 35-levels at the output with a reduced total harmonic distortion (THD). The developed topology requires a lesser number of switches with fewer switching losses compared with other similar topologies. As the proposed MLI consists of a lesser switch count, the respective driver circuits and the total number of components of the circuit becomes less, hence the size and cost of the MLI get reduced. The modulation scheme incorporated in the proposed MLI is the staircase modulation technique. The developed MLI is tested for various loads such as R, L and combinational loads like R-L and l -R, also the MLI is tested with dynamic load variations and found to be stable throughout the operation of the MLI. The simulation of the developed MLI is done using MATLAB/Simulink and the experimental results are validated with a hardware prototype with a dSPACE RTI1104. The outcomes of the proposed 35-level MLI are compared with the several conventional and existing modern topologies with various parameters and found to be efficient in its operation. The suggested 35-level inverter is quite suitable for Hybrid /Full electric vehicles (HEV) and medium or high voltage/power applications.

A Simple Staircase Modulation for A Cascaded H-bridge Multilevel Inverter

This paper proposes a novel simple staircase modulation to obtain reasonable performance of an output voltage for a cascaded HBridgemultilevel inverter. The motivation of the proposed algorithm is that the inverter phase voltage intersects with an original sinusoidalwaveform at equal points in the y-axis. This modulation technique can calculate the independent switching angles more simply than thetraditional method, which employed Fourier’s series analysis, and can be applied to all kinds of multilevel inverters. In this paper, for the sake of validation, the technique was applied to a cascaded H-bridge inverter with unequal DC sources. Then, it was applied to the seventh, ninth, eleventh, and twenty-seventh levels of the multilevel inverter. In addition, pulse width modulation techniques used in this type of multilevel inverter are complicated. The PSIM software program was used for all simulation examples, and its results are consistent with the experimental results.

Staircase modulation improvement to balance output power of stages of cascade H-bridge multilevel inverter

In this study, different methods are investigated to minimize the power imbalance between the stages of a cascade H-bridge (CHB) multilevel inverter (MLI). First-in-first-out (FIFO) and first-in-last-out (FILO) are two common staircase-modulation (SCM) methods. A CHB-MLI with FIFO modulation, even with the same conduction times, cannot distribute power equally between the stages. A new algorithm is presented in this study to balance the power between the inverter stages. This is important to increase the lifetime of the PV sources that feed the inverter. To implement the new algorithm, all possible switching patterns based on the angles obtained from the nearest level of control (NLC) method are defined as the sample spaces of random variables. Subsequently, a random vector is defined for a set of random variables, and an optimization problem with finite and discrete solutions is applied. This algorithm is effectively used to minimize the power imbalance between the stages, even in impedance loads, from the purely inductive to the pure capacitive range. In addition, with slight changes in the switching angles, the operation of the stages and the inverter efficiency increases. Finally, the simulation and experimental results confirm the validity and practicality of the proposed modulation.

Frequency spectra based approach to analytical formulation and minimization of voltage THD in staircase modulated multilevel inverters

Staircase Modulation (SCM) is a popular switching strategy for multilevel inverters (MLI), which is often a preferable alternative to Pulse Width Modulation (PWM) due to its reduced switching losses, especially for MLIs with a relatively high number of voltage levels (N). In some applications, such as motor drives, or when output filters are applicable, SCM may also suit MLIs with moderate N values. While MLIs with Equal DC Sources (EDCS) are more common, MLIs with Unequal DC Sources (UDCS), such as asymmetric Cascaded H-Bridge (CHB) MLIs are known to further reduce the waveforms’ Total Harmonic Distortion (THD). The main objective of SCM is to adjust the waveform’s fundamental component, while employing some harmonic mitigation strategy, such as THD minimization. Such an optimization approach relies on an accurate THD formulation, which eliminates underestimation errors associated with numerical THD approximations. This paper reveals novel generic analytical formulations of both Phase-voltage THD (PTHD) for single-phase MLIs and Line-voltage THD (LTHD) for three-phase MLIs. The revealed exact formulation approach is derived from Fourier series representation of THD, resulting in simple closed-form PTHD and LTHD expressions, applicable to any MLI topology, with either EDCS or UDCS configurations, and arbitrary value of N (odd and even). Given an arbitrary N value, the proposed formulations can be used to generate symbolic N-level PTHD or LTHD expressions, which are symbolic functions of the Phase Switching Angles (PSA) and (optionally) the DC source Ratios (DCR). The revealed THD formulations are verified and compared against recently introduced time-domain-based THD formulations. It is shown that when both time and frequency-based formulations are employed in THD minimizations to form a novel Hybrid Temporal-Spectral (HTS) Optimal Minimization of THD (OMTHD) approach, even better results can be achieved. The novel OMTHD is deeply explored and verified by both digital simulations and Controller + Hardware in Loop (C-HIL) based real-time experiments using 7- and 8-level three-phase MLI configurations. A downloadable supplemental file containing Maple and MATLAB functions of the proposed THD expressions, as well as pre-calculated sets of optimum variables for different values of N is provided for readers' convenience.

Compare the Symmetric Hybridized Cascaded MLI with 17 levels with the Asymmetric Switched Capacitor MLI Topologies for Dynamic Loading

This article builds a symmetric hybridized cascaded a switching capacitor unit in a multilayer inverter and compares it to For 17 level inverters, A switched capacitor unit is utilized with an asymmetric multilevel inverter. In the symmetric hybridized multilevel inverter design, a In the midst of a dual-input dc source, there is a bi-directional switch is utilized to create a modified H-bridge inverter with a five-level output voltage instead of three. In the proposed scenario, In an asymmetric multilevel inverter, the switched capacitor unit substitutes the dc sources. which enlarges By a factor of two, The output voltage has been increased. and the voltage levels at the loads are increased by a factor of two. MATLAB-SIMULINK was used to verify the suggested topology using the staircase modulation approach. The findings show that multilayer inverter topologies with low total harmonic distortion, fewer switches, With greater levels of output voltage are better stable during load disturbance circumstances, making them ideal for renewable energy applications.

A Modular Concept Development for Resonant Soft-Charging Step-Up Switched-Capacitor Multilevel Inverter for High-Frequency AC Distribution and Applications

This article presents a step-up switched-capacitor (SC) multilevel inverter (MLI) with reduced ripple power loss by employing a soft-charging technique and modular cell. SCMLI possesses many attractive features for high-frequency ac (HFAC) applications. With a two-phase alternating structure, the voltage ratings of the components in the proposed SCMLI are substantially reduced compared with the unfolding H-bridge-based topologies while preserving the features of voltage step-up and self-voltage balancing offered by the series-parallel SC method. This structure also enables higher operating frequency by extending the maximum charging duration of capacitors. By inserting a small resonant inductor, soft-charging is achieved in all SC units in the inverter which mitigates the ripple loss and electromagnetic interference issues existing in many SCMLIs. The soft-charging operation of the proposed inverter under staircase modulation is elucidated based on the theory of underdamped SC circuit. The mathematical analysis is validated by the simulation and experimental outcomes showing a dramatic reduction in the ripple power loss by employing the soft-charging technique. The technique is highly suitable for high-frequency power distribution.

Staircase Modulation For Thirteen Level Cascaded H Bridge Inverter With Different Staircase Wave Generation Techniques

This paper intended a staircase modulation with different staircase generation for a thirteen level cascaded H bridge inverters. Staircase modulation scheme is developed to achieve the control of MLI. Here paper discusses various staircase wave generation methods such as half height (HH) method, Half Equal Phase (HEP) method and Feed Forward (FF) method to find step size of staircase wave. The analysis of different staircase waves in control of MLI is carried out with an thirteen level cascaded H Bridge Multilevel inverter using phase shift carrier modulation. The expected methods results in staircase reference wave generation with lesser THD compare to other convectional MLI. The performance of 13 level CHN with different staircase reference signal is analyzed in terms of THD through extensive simulations and by comparing these three staircase reference signal generating methods, it is clear that HH method show lesser THD.

An enhanced 17-level hybridized multilevel inverter with stair case modulation

This paper proposes a Hybridized Symmetric Cascaded Multilevel Inverter for voltage levels ranging from 5 levels to 17 levels. The proposed Multi Level Inverter (MLI) topology is built using a modified H-bridge inverter that results in an increased output voltage levels with a smaller number of solid-state switches. This technique enhances the h-bridge configuration from three level to five level by means of a bi-directional switch at source. Gating pulses of hybridized symmetric MLI are generated through staircase modulation. The operation and performance of the proposed topology is tested for different output voltage levels, simulation results prove that the proposed technique results in less THD at all levels with lesser power consumption and are easily applicable for renewable energy applications.

Analytical formulation and optimization of Weighted Total Harmonic Distortion in three-phase staircase modulated multilevel inverters

Staircase Modulation (SCM) is a popular switching strategy for three-phase multilevel inverters (MLI) of higher voltage levels count (N). SCM is often combined with some harmonic mitigation strategy, such as a minimum of Total Harmonic Distortion (THD) in addition to output fundamental component adjustments. While voltage THD-based SCM is desirable in many applications, it is not a panacea for all applications, especially for motor drives and grid-connected MLIs, where minimization of current-THD is preferable. A THD alternative performance parameter, called frequency-Weighted Total Harmonic Distortion (WTHD) can serve as a strong indication of current-THD, especially in inductive loads. For three-phase MLIs with 3-wire loads, line voltage waveform has more significance than phase voltage waveform, as it directly impacts the load’s current quality. For this reason, the minimization of Line-voltage WTHD (WLTHD) may be preferred over the minimization of THD, Line-THD (LTHD) or WTHD. Since WLTHD involves complicated expressions, it is typically calculated and expressed using frequency-domain numerical approaches, often resulting in underestimation errors. In this paper, a novel analytical WLTHD formulation for three-phase SCM-based MLIs is revealed and used for subsequent WLTHD minimization with the aim of minimizing load current-THD for 3-wire inductive loads. The proposed WLTHD formulation is a function of all possible Phase Switching Angles (PSA), valid for any MLI topology with arbitrary values of N, either odd or even. Moreover, it is shown that the existing WLTHD minimization approach is a particular case of the proposed generic methodology. The derived formulation, which can produce mathematically exact symbolic WLTHD results, is verified against numerically obtained results in previous works. Controller + Hardware in Loop (C-HIL) based validation is also carried out for 7-level three-phase MLIs feeding an induction motor for current-THD optimization, revealing significant improvements compared to previously obtained methods. The proposed WLTHD minimization possess the highest correlation to current-THD, even for nearly resistive loads. Links for downloading MATLAB and Maple source files of proposed WLTHD formulations as well as pre-calculated optimum PSA results for 5 ≤ N ≤ 16, covering most of the practical cases, are also provided for reader’s convenience.

A novel algorithm for increased power balance in cascaded H-bridge multilevel cells in a hybrid power amplifier

This paper concerns the issue of unbalanced output power among cells in cascaded H-bridge multilevel (CHBM) converters with conventional staircase modulation techniques under low modulation signals. This is a common condition in high-voltage/frequency hybrid power amplifiers (HPAs) consisting of a CHBM converter in series with a linear power amplifier (LPA). The online implementation of a modulation technique called split-voltage first-in first-out (SV-FIFO) that mitigates this issue is presented in this study. Differently from conventional techniques, it needs to take into consideration the magnitude and frequency of the reference voltage to generate the gating signals of the CHBM converter. This paper also introduces a design procedure for a series-type HPA and a means for generating online the gating signals of the CHBM converter, with SV-FIFO, and the reference signal for the LPA in closed loop with a mixed signal controller. Experimental results for a series-type HPA with a six-cell CHBM converter and a commercial LPA are provided to validate the design procedure of the HPA and demonstrate the enhanced (active) power balance of SV-FIFO and the effectiveness of the proposed control scheme for the HPA under transient and steady-state conditions.

A Novel Multilevel DC-Link Three-Phase T-Type Inverter

This research proposes a four-level T-type inverter that is suitable for low-power applications. The presented topology outranks other types of inverters in terms of a smaller number of semiconductor devices, absence of passive components such as clamping diodes and flying capacitors, low switching and conduction losses, and high efficiency. The proposed topology is free from voltage deviation and unbalanced voltage occurrences that are present in other multilevel converters having clamping diodes or flying capacitors. The proposed inverter can extend to N levels using unequal dc-link voltage sources for medium-voltage application. The inverter employs the simple fundamental frequency staircase modulation technique. Moreover, this paper presents a current commutation strategy to prevent the occurrences of short circuit and minimizing the number of required switching devices and switching transitions, resulting in improving the efficiency of the inverter. This paper also analyses the theoretical converter losses showing lower switching and conduction losses when compared to existing four-level inverters. The experimental validation of the proposed inverter shows its operating feasibility and a low output voltage THD.

Nonzero Staircase Modulation Scheme for Switching DC-DC Boost Converter

This paper presents a novel modulation scheme known as the nonzero staircase modulation scheme for switching DC-DC boost converters. This modulation scheme generates two distinct pulse trains/firing signals when a 50 Hz nonzero staircase modulating signal is compared with a 1.5 kHz triangular wave signal. Unlike the conventional modulation schemes, the proposed novel modulation scheme provides two distinctive trains of pulse-width modulated signals for mitigating low and high harmonics. It also possesses 0.56% total harmonic distortions (THD) of the output voltage waveform system, a power output of 4591 W, and THD of 1.12% in the DC-DC boost converter system. It has a simple design and low power loss of 209 W. The proposed scheme enables the single switch boost DC-DC converter used to have an efficiency of 96%. The proposed scheme can be applied in single switch or double switch boost DC-DC converter based-hospital equipment.

Controller Design and Implementation of Solar Panel Companion Inverters

A solar panel companion inverter (SPCI) is a single-stage dc-ac power converter, installed with each solar panel. Each SPCI synthesizes an ac quasi-square wave voltage with variable pulsewidth. The width of ac output voltage of each SPCI is proportional to available power on the solar panel. Output voltages of SPCIs are aggregated across multiple solar panels connected in series, and a sinusoidal ac voltage is synthesized. In this article, dynamic analysis and closed-loop current controller design of SPCI is presented. Simulation results demonstrating the dynamic response of the closed-loop SPCI are included. The closed-loop current control scheme is implemented on a hardware prototype to demonstrate the grid-tied operation of SPCI, and experimental results are presented. A maximum power point tracking (MPPT) algorithm is implemented for sorted stair-case modulation (SSCM) in MATLAB Simulink. Experimental results demonstrating MPPT operation are presented.

Analytical Formulation and Minimization of Voltage THD in Staircase Modulated Multilevel Inverters With Variable DC Ratios

Staircase Modulation (SCM) is a commonly employed switching strategy in Multilevel Inverters (MLI) with a high number of voltage levels (N). The main challenges in SCM are adjusting the Modulation Index (MI) to the desired value while minimizing the Total Harmonic Distortion (THD). This is achieved by solving an objective function for its optimum variables. These variables are the Switching Angles (SA) in the case of an MLI with Equal DC voltage Supply (EDCS), or both the SAs and the DC voltage supply Ratios (DCR), in the case of an MLI with Unequal DC voltage Supply (UDCS). Such an approach, which is referred to as Optimum Minimization of THD (OMTHD), relies on the accuracy of the THD expression used for the objective function. This paper reveals generic analytical closed-form formulations of both Phase-voltage THD (PTHD) for single-phase (1φ) MLIs and Line-voltage THD (LTHD) for three-phase (3φ) MLIs. The revealed THD expressions apply to SCM based MLIs of any topology, with either EDCS or UDCS voltage source configurations, which may be fixed or varying, and arbitrary value of N (odd and even). Given an arbitrary N value, the proposed unified formulations can be used to generate symbolic N-level PTHD or LTHD expressions, which are analytical functions of the SA and (optionally) DCR variables. The proposed THD expressions were used to form a generic OMTHD problem and solve for optimum SA and DCR variables, ensuring PTHD or LTHD minimization, subject to a set of optional constraints, such as the target MI, tolerable Modulation Error (ME), and the Maximum DCR (MDCR). Outcomes of the proposed OMTHD algorithm were successfully verified by Controller + Hardware-in-Loop (C-HIL) based experiments and compared against results of previous works, raveling significant improvement in THD accuracy and MLI's performance. A downloadable supplemental file containing Maple and MATLAB functions of the proposed THD expressions, as well as pre-calculated sets of optimum SAs and DCRs tables for 13 different values of N (4 ≤ N ≤ 16), is provided for readers' convenience.

Compact Three Phase Multilevel Inverter for Low and Medium Power Photovoltaic Systems

A new three phase multilevel inverter with reduced number of components count is proposed in this paper. This inverter is designed using a single DC source per phase to generate multiple level output voltage which makes it suitable for low and medium voltage applications, including ac-coupled renewables or energy storages. A generalized circuit configuration is shown in this paper following which the number of output voltage level can be increased as per expectation. Although, each element endures the voltage stress equivalent to the input DC voltage, the value of total standing voltage (TSV) is reduced by the utilization of minimized number of components with respect to the number of series connected capacitors. Further, staircase modulation scheme is used to generate the switching signals. Hence, the proposed inverter can be operated at low switching frequency with optimal output current harmonic distortion which decreases switching losses and suppresses power factor falling. In order to validate the theoretical explanations and practical performances of the proposed inverter, the hypothesis is simulated for 9, 13 and 39 output voltage level inverters for three phase with a line voltage total harmonic distortion (THD) of 6.06%, 4.16% and 2.10% respectively in MATLAB/Simulink and a 5-level single phase laboratory prototype is implemented in the laboratory.