Design and implementation of a novel 35-level inverter topology with reduced switch count

Abstract

• A novel 35-level multilevel inverter is designed with reduced switch count. • Experimental investigation is carried out with dynamic load changes. • Performance of the proposed inverter is evaluated with various parameters. • The proposed inverter is cost-effective with lower total standing voltage. • The proposed inverter has reduced power losses with improved efficiency of 93.37%. This paper projects a novel topology for the 35-level MLI. The proposed topology aims to generate 35-levels at the output with a reduced total harmonic distortion (THD). The developed topology requires a lesser number of switches with fewer switching losses compared with other similar topologies. As the proposed MLI consists of a lesser switch count, the respective driver circuits and the total number of components of the circuit becomes less, hence the size and cost of the MLI get reduced. The modulation scheme incorporated in the proposed MLI is the staircase modulation technique. The developed MLI is tested for various loads such as R, L and combinational loads like R-L and l -R, also the MLI is tested with dynamic load variations and found to be stable throughout the operation of the MLI. The simulation of the developed MLI is done using MATLAB/Simulink and the experimental results are validated with a hardware prototype with a dSPACE RTI1104. The outcomes of the proposed 35-level MLI are compared with the several conventional and existing modern topologies with various parameters and found to be efficient in its operation. The suggested 35-level inverter is quite suitable for Hybrid /Full electric vehicles (HEV) and medium or high voltage/power applications.