Stage Amplifier Research Articles

A Compact 60GHz Power Amplifier in 65nm CMOS Technology

A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stage impedance matching as well as input and output matching. The compact structure of on-chip transformer can reduce the chip size and improve the integration degree. The measured small signal gain at 60GHz of 22.3dB, the saturation power of 20.2dBm, the output P-1dB of 17.3dBm, the PAE of 14%, and the core area is 0.19mm2. The power amplifier can be used in high-speed short-range wireless communication system to enhance communication data transmission capacity.

Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology

<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

Optical absorption tomography for temperature and H2O concentration imaging by a compact photoelectric detecting system combined with twice adaptive algebraic algorithm

Tunable diode laser absorption spectroscopy is a robust method for simultaneous measurements of temperature and gas species. Different from commercial detectors integrated with photodiode receivers and amplifiers as the detecting system, a custom-made photoelectric detecting system comprised of Ge detectors and separated amplifiers was designed. First, Ge detectors received optical power from laser beams and then converted it into electrical current signals. The trans-impedance amplifiers were used to convert the current signals to voltage signals. The second stage amplifiers further amplified the voltage signals. All amplifiers that integrated the electronic circuits were packed in a portable case. Finally, the amplified voltage signals were received by data acquisition card. In this way, detectors could be arranged more compact and are easier to facilitate expandability. In addition, absorption data were reconstructed using twice adaptive algebraic reconstruction technique (AART) algorithm. During the reconstruction, after obtaining the temperature distribution through AART algorithm, AART algorithm was adopted for the second time for H2O concentration distribution. This system was validated with measurements of one-dimensional average temperature in a high temperature tube furnace and the system combined with twice adaptive algebraic algorithm demonstrated in a square flow field containing McKenna burners for simultaneous measurements of temperature and H2O distribution. The results indicated the viability and potential of this system combined with twice adaptive algebraic algorithm for sensitive temperature and H2O distribution tomography.

2차 고조파 최소화를 위한 광대역 중간주파수신기 개발

In this study, an eight-channel wide-band intermediate frequency (IF) receiver with an S-band input frequency, an output frequency of 200 MHz, and a signal bandwidth of 160 MHz was developed. The performance measurement results of the IF receiver showed that the fundamental signal and the second harmonic signal were involved in the bandwidth of the IF receiver output. This was caused by the nonlinearity characteristics of the final stage amplifier. Therefore, the final stage amplifier was changed to a differential amplifier, and the circuit of the IF receiver was modified to reduce the second harmonic signal. After improvement, an IF receiver with a gain of 33 dB, Output 1 dB Gain Compression Point(OP1dB) of > 15.8 dBm, 3rd Output Intercept Point(OIP3) of > 25.7 dBm was developed. The second harmonic suppressions were in the range of −83.30 dBc to −75.19 dBc when the fundamental signal output power was −10 dBm. This result satisfied the requirement of the system for the second harmonic suppression that was lower than −70 dBc.

Design of high speed 2-stage OTA for high capacitive load of 120 pF and 2.96 V

High speed operational transconductance amplifier (OTA) is used to drive high capacitive loads to reduce the charging time while providing adequate gain and stability. A 2-stage amplifier is proposed to provide high slew rate and sufficient gain and stability. 45 nm process technology is used to compare performance with differential and telescopic amplifier designs. Resistive feedback and noise-gain compensation techniques are used to drive 120 pF load of a row driver circuit used in an active pixel sensor and provide 2.96 V at output for a high slew rate of 2.2 V/μs.

Improved reversed nested miller frequency compensation techniques using flipped and folded flipped voltage follower with resistor for three stage amplifier

This paper presents three circuits to improve frequency compensation in three stage amplifier for large capacitive load of 100 pF. The first proposed circuit introduces Flipped Voltage Follower (FVF) in inner loop of Reversed Nested Miller Compensation (RNMC) to combat RHP zero whereas both second and third proposed circuits employ A Folded Flipped Voltage Follower (FFVF). The third proposed circuit uses an additional resistor in the outer compensation loop for double pole-zero cancellation. Further feed forward path has been used in all proposed circuits to improve the large signal response. The functionality is verified using TSMC 0.18 µm CMOS technology parameters in Tanner tool. The simulation results show maximum gain-bandwidth product (GBW) of 30 MHz, minimum phase margin (PM) of 60° and slew rate (SR) of 10 V/µS, and minimum common mode rejection ratio (CMRR) of 37.2 dB at unity gain frequency. The input-referred noise of the proposed circuits varies from 16.6 nV/Hz to 18.2 nV/Hzat unity gain frequency. Corner analysis is also included to show the robustness of the circuits.

Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis

Several automatic analog integrated circuit (IC) sizing tools have been proposed and successfully applied to multi-objective circuit design problems over the last two decades. However, rendering those tools yield-aware has not been fully addressed yet since inclusion of variability analysis to the optimization loop is still a bottleneck due to the tremendous trade-off between accuracy and efficiency of the synthesis process. Conventional Monte Carlo (MC) based approaches are quite accurate, but, they are highly inefficient due to cumbersome simulation effort. Even though employing enhanced sampling techniques, e.g., Latin Hypercube Sampling (LHS), exhibits slightly better efficiency, the accuracy of such approaches is still less than Monte Carlo. To palliate this problem, in this paper, we propose a novel Deep Neural Network (DNN) aided MC simulation framework for yield-aware analog circuit sizing. In the developed tool, the DNN is leveraged to develop circuit models during the optimization, which are then used to estimate the effects of variations in device dimensions without any simulation effort while some additional simulations are concurrently carried out for Vth variations. Finally, once DNN based circuit models are obtained, the simulator is replaced by those models during the MC analysis, which enables performing expanded MC for accurate yield estimations without running any simulations. To demonstrate the developed tool, three analog circuits were optimized, a single stage-active loaded amplifier, a two stage amplifier, and a voltage comparator. According to the synthesis results, the proposed approach can achieve up to 96.61% reduction in overall execution time (29x speed-up).

Characterization of a flux-driven Josephson parametric amplifier with near quantum-limited added noise for axion search experiments

The experimental non-observation of charge-parity (CP) symmetry violation in quantum chromodynamics is commonly referred to as the strong CP problem. The axion, a hypothetical elementary pseudoscalar, is expected to solve the strong CP problem and is also a promising candidate for dark matter. The most sensitive axion search experiments operate at millikelvin temperatures and hence rely on instrumentation that carries signals from a system at cryogenic temperatures to room temperature instrumentation. One of the biggest limiting factors affecting the parameter scanning speed of these detectors is the noise added by the components in the signal detection chain. Since the first amplifier in the chain limits the minimum noise, low-noise amplification is of paramount importance. This paper reports on the operation of a flux-driven Josephson parametric amplifier (JPA) operating at around 2.3 GHz with added noise approaching the quantum limit. The JPA was employed as a first stage amplifier in an experimental setting similar to the ones used in haloscope axion detectors. By operating the JPA at a gain of 19 dB and cascading it with two cryogenic amplifiers operating at 4 K, noise temperatures as low as 120 mK were achieved for the whole signal detection chain.

Nonlinear spectral-phase-engineering strategies via quasiparametric chirped-pulse amplification

Ultrafast petawatt laser facilities require pulse compression strategies to deal with high-order dispersions. The third-order dispersion and especially the fourth-order dispersion need special compensation techniques. Quasiparametric amplification (QPA) has shown many benefits, such as high efficiency, and can bear the phase mismatch. In this paper we discuss the high-order dispersions induced in quasiparametric amplification and show the potential of the quasiparametric preamplifier with negligible pump depletion as a high-efficiency nonlinear phase compensator. We also discussed the high-order dispersions in QPA as a final stage amplifier where the pump is totally depleted and studied how those dispersions finally affect the amplified signal pulses.

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

An ultra low-power ECG amplifier for wearable devices using classical 2-stage OTA

Wearabl smart devices have become an important method to monitor people’s health. This research work aims to offer a relatively optimum solution to amplify the biomedical signal in the case of wearable devices. This is done by using the single-stage amplifier and Operational Transimpedance Amplifier (OTA) stage. The OTA stage uses a typical 2-stage amplifier topology, with first-stage differential pair, second stage a common source to provide high-gain. Simulation results showed that the amplifier has a differential gain of 40.04dB, a total integrated input-referred noise of 3.59uVrms, a total power consumption of 1.44uW, a NEF of 21 and a CMRR of 82 dB. In conclusion, the results verify the single-stage amplifier topology is useful and satisfy the low-power requirement.

Novel Design Charts for Optimum Source Degeneration Tradeoff in Conjugately Matched Multistage Low-Noise Amplifiers

Source degenerative feedback is extensively applied in the low-noise amplifier design. The beneficial effects of this technique are well established in the open literature. However, the designer is often left to trial-and-error or optimization procedures to identify the adequate amount of feedback when other linear requirements, such as signal matching, come into play. This issue is even more relevant in multistage designs. In this article, we present a synthesis procedure and the relevant design chart to identify the optimum feedback inductor value on all transistors of an $N$ -stage amplifier to obtain a perfect match at its external ports in conjunction with amplifier noise figure minimization and a specified gain requirement. It is shown that the method is applicable to arbitrary $N$ values although it becomes more elaborate for $N$ greater than 6. The method is deterministic as opposed to optimization or trial-and-error-based procedures. The design flow is illustrated at first through a four-stage design with ideal matching elements and subsequently validated by an monolithic microwave integrated circuit (MMIC) test vehicle designed and realized in the WIN foundry’s Gallium Arsenide PIH1-10 process. The measured performance of the test vehicle is NF = 1.9 dB, 26 dB gain, typical I/O return loss of 15 dB in the 26.5–29.5-GHz bandwidth, and practically ideal behavior at the design frequency of 28 GHz.

An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Characterization of MEMS Acoustic Sensors and Amplifiers in Cryogenic Fluids for Quench Detection Applications in HTS CICC

An acoustic quench detection method utilizing MEMS (Micro Electro-Mechanical System) acoustic sensors is proposed. To investigate this method, a commercially available MEMS piezoelectric microphone, the Vesper VM1000, and two types of second stage amplifiers, using either an OPA344 or a LMH6629 based amplifier circuit, were characterized at cryogenic temperatures in helium gas. The MEMS microphones were in their original package with an integrated preamplifier. The tests were performed inside a two-stage Gifford-McMahon cryocooler from room temperature down to 60 K, at static pressures between 1.2 and 1.4 bar in gaseous helium, over the frequency band from 100 Hz to 10 kHz. Second stage amplifiers were needed to achieve signal to noise ratios approaching the manufacturer specified operating levels. The OPA344 based amplifier reduced in gain by >55 dB below 230 K, while the LMH6629 based amplifier performed well down to 60 K. The MEMS microphones appear to perform acoustic measurements down to 165 K but with some reduction in sensitivity down to 60 K. An acoustic model of the cryocooler plane wave tube calibration setup is developed and used to calibrate the microphone despite the presence of a significant thermal gradients down the plane wave tube.

Single frequency vertical piezoresponse force microscopy

Piezoresponse force microscopy (PFM) uses a cantilever arm to track the electromechanical motion of the electric dipole moment to visualize the ferroelectric domain structure, which provides an important insight into the physics of switchable electric polarization—especially for memory devices and integrated microelectronics. Here, I provide a tutorial on single frequency vertical PFM, the most basic mode of PFM. I will start with the basic components of atomic force microscopy (AFM), including tip, cantilever, X–Y stage, Z actuator, and lock-in amplifier. Contact mode AFM will be briefly explained and discussed, where you can find two modes: constant deflection and constant height modes. Single-frequency vertical PFM splits the frequency domain of tip vibration into low and high frequencies and uses a low-pass filter to nullify any motion caused by topography (constant deflection). In contrast, the lock-in amplifier will pinpoint the vibration induced by the vertical piezoelectric strain along the sample’s surface normal (constant height). This tutorial will provide an overall and detailed step by step instruction to conduct PFM imaging and piezoresponse hysteresis loop measurement using atomic force microscopy and a lock-in amplifier and teach how to interpret the PFM images and the piezoresponse hysteresis loops for various applications.

A new measurement algorithm for TDR-based localization of large dielectric permittivity variations in long-distance cable systems

One of the most common applications of time-domain reflectometry (TDR) is the localization of dielectric permittivity variations (DPVs) along cable systems. However, signal attenuation and dispersion phenomena limit the usability of TDR when used on long cable systems. Some TDR measuring instruments offer the possibility of modifying the amplitude and the width of the TDR test pulse signal, along with the gain of the input stage amplifier. Increasing these parameters generally allows to investigate longer distances; nevertheless, increasing the gain may saturate the instrument analog to digital converter (ADC) and increasing the pulse width leads to worse spatial resolution. For this reason, it is customary for the operator to repeat TDR measurements several times, with different settings, and proceed by focusing each time on a different TDR reflectogram; however, this procedure is time-consuming and, eventually, it does not guarantee optimal performance.Starting from these considerations, in this work, a new measurement algorithm for facilitating and making more effective the TDR-based localization of large DPVs on long cable systems is proposed. The algorithm automatically acquires several TDR reflectograms obtained by setting different values of the gain of the input stage amplifier and the values of the pulse width of the test signal. The reflectograms are then automatically processed, in an effort to balance the short-distance resolution and long-distance gain in a single composite reflectogram (CR), which can be conveniently used also by non-skilled operators. The developed algorithm was implemented and validated through experiments on a practical case study to localize DPVs on a 300 m-long cable system.

Design and Analysis of 2N4416 n channel JFET Single Stage Amplifier for large band width and low Voltage Gain

A bipolar junction transistor (BJT) is a current-controlled device, while a field-effect transistor (FET), is a voltage-controlled device, the bipolar transistor has two principal disadvantages. First, it has low input impedance because of the forward-biased emitter junction. Secondly, it has a considerable noise level. The field-effect transistor (FET) has a large input impedance which may be more than 100 megaohms, the FET is generally much less noisy than the ordinary or bipolar transistor. In this paper 2N4416 n channel JFET single-stage amplifier was designed, in order to analyze the circuit, important terms and main parameters were determined, the frequency response and bandwidth of the amplifier were also determined and discussed graphically using Multisim 14.2 simulator, the results characterized amplifier with large bandwidth and low voltage gain.

High-temperature reliability of integrated circuit based on 4H-SiC MOSFET with Ni/Nb ohmic contacts for harsh environment applications

The high-temperature reliability of integrated circuit based on 4H-SiC MOSFET with Ni/Nb ohmic contacts was investigated at 400 °C in N2 ambient. The results showed that the single stage amplifier remained a stable voltage gain after 100 h of aging at 400 °C. Based on the transfer length method, the Ni/Nb/n-type 4H-SiC ohmic contact exhibited the excellent stability after being aged at 400 °C for 100 h. Whereas, the stability of electrical characteristics indicated that the 4H-SiC MOSFET also exhibited a good stability when operating in high temperature environment. Moreover, the stability of the electrical characteristics of the 4H-SiC MOS capacitor showed that the reliability of the Ni/Nb/4H-SiC ohmic contact played important role in reliability of SiC based devices. These results indicate that the fabrication process of the integrated circuits based on 4H-SiC devices with Ni/Nb ohmic contacts is promising to apply for high temperature as well as harsh environment applications.

3 mJ All-Fiber MOPA With a Short-Length Highly Er3+-Doped Phosphate Fiber

A very large mode-area 2 wt% erbium-doped double-clad phosphate fiber with a core diameter of 60 μm and core numerical aperture of 0.03 was fabricated and used for the last stage amplifier of an all-fiber pulsed laser master-oscillator power amplifier (MOPA) at 1550 nm. The Er <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3+</sup> double-clad phosphate fiber has a cladding-core ratio of 2.17 and a V number of 3.6 at 1550 nm. 3 mJ pulses with 21.5 ns duration were obtained with Gaussian-like spatial beam profile with only a 75 cm long phosphate gain fiber.

A Configurable Noise-Shaping Band-Pass SAR ADC With Two-Stage Clock-Controlled Amplifier

This article presents an $8\times $ -oversampling successive approximation register (SAR) analog-to-digital converter (ADC) with configurable center frequency of noise shaping (NS), which permits the signal passband being configured to any one of the 8 equally divided sub-bands in the first Nyquist band. The configurable noise shaping is realized by an error-feedback (EF) structure with an adjustable 2-tap switched-capacitor (SC) FIR filter. Taking advantage of the sub-bands’ symmetry, the selection of the 8 sub-bands are determined by only a 2-bit controlled variable capacitor in the FIR filter in addition to one bit indicating which half-band the target sub-band is in. As a result, the configuration circuit is area efficient and introduces very little parasitic into the critical EF path. A 2-stage clock-controlled amplifier (CAMP) is proposed for the EF path, which can ensure gain and speed simultaneously through allocating reasonable currents into the gain stage and the driving stage separately. Implemented in 65-nm CMOS process, measurement results under a sampling rate of 10 MSPS show that the prototype achieves signal-to-noise-and-distortion (SNDR) of 71.9~74.6 dB in the 8 sub-bands with 625-KHz bandwidth, corresponding to a Scherier FoM of 171.4 -174 dB. The ADC prototype occupies 0.03-mm2 core area and consumes 70- $\mu \text{W}$ average power at 1-V supply voltage.