Stacked Silicon Nanowire Research Articles

Highly Photoresponsive Vertically Stacked Silicon Nanowire Photodetector with Biphasic Current Stimulator IC for Retinal Prostheses

This paper presents an integrated approach for a retinal prosthesis that overcomes the scalability challenges and limitations of conventional systems that use external cameras. Silicon nanowires (SiNWs) are utilized as photonic sensors due to their nanoscale dimensions and high surface-to-volume ratio. To enhance these properties and achieve high photoresponsivity, our research team developed a vertically stacked SiNW structure using a fabrication method entirely based on dry etching. The fabricated SiNW photodetector demonstrated excellent electrical and optical characteristics, including linear I–V characteristics that confirmed ohmic contact formation and high photoresponsivity exceeding 105 A/W across the 400–800 nm wavelength range. The SiNW photodetector, following its integration with a switched capacitor stimulator circuit, exhibited a proportional increase in stimulation current in response to higher light intensity and increased SiNW density. In vitro experiments confirmed the efficacy of the integrated system in inducing neural responses from retinal cells, as indicated by an increased number of neural spikes observed at higher light intensities and SiNW densities. This study contributes to sensor technology by demonstrating an approach to integrating nanostructures and electronic components, which enhances control and functionality.

Ultra-Confined Catalytic Growth Integration of Sub-10nm 3D Stacked Silicon Nanowires Via a Self-Delimited Droplet Formation Strategy.

Fabricating ultrathin silicon (Si) channels down to critical dimension (CD) <10nm, a key capability to implementing cutting-edge microelectronics and quantum charge-qubits, has never been accomplished via an extremely low-cost catalytic growth. In this work, 3D stacked ultrathin Si nanowires (SiNWs) are demonstrated, with width and height of Wnw = 9.9 ± 1.2 nm (down to 8nm) and Hnw = 18.8 ± 1.8 nm, that can be reliably grown into the ultrafine sidewall grooves, approaching to the CD of 10nm technology node, thanks to a new self-delimited droplet control strategy. Interestingly, the cross-sections of the as-grown SiNW channels can also be easily tailored from fin-like to sheet-like geometries by tuning the groove profile, while a sharply folding guided growth indicates a unique capability to produce closely-packed multiple rows of stacked SiNWs, out of a single run growth, with the minimal use of catalyst metal. Prototype field effect transistors are also successfully fabricated, achieving Ion/off ratio and sub-threshold swing of >106 and 125mV dec-1 , respectively. These results highlight the unexplored potential of versatile catalytic growth to compete with, or complement, the advanced top-down etching technology in the exploitation of monolithic 3D integration of logic-in-memory, neuromorphic and charge-qubit applications.

Investigation of Self-Heating Effects in Vacuum Gate Dielectric Gate-all-Around Vertically Stacked Silicon Nanowire Field Effect Transistors

The self-heating effects in vacuum gate dielectric gate-all-around field effect transistors (GAA FETs) with vertically stacked 4-nm silicon nanowire (SiNW) channels are investigated by 3-D TCAD simulation. The cross-sectional dimension-dependent thermal conductivity model of the SiNW is proposed for the precise numerical simulation of self-heating effects based on the temperature-dependent thermal conductivity of the bulk silicon. The thermal conductivity model which was verified by published data indicates that thermal conductivity of 4-nm SiNW is greatly reduced to below 10 W/mK due to the pronounced phonon boundary scattering. Simulation results shows that the vacuum gate dielectric devices undergo more severe self-heating effects than the solid gate dielectric GAA SiNW FETs, resulting in more serious performance degradation. Multiple heat sources generated by the three-stacked SiNWs make heat generation and diffusion more difficult. An effective method is proposed to suppress the self-heating effects by increasing the spacing of the gas gap within in a certain range and the around ambient gas pressure.

Investigation of Self-Heating Effects in Gate-All-Around MOSFETs With Vertically Stacked Multiple Silicon Nanowire Channels

The self-heating effects (SHEs) in gate-all-around (GAA) MOSFETs with vertically stacked silicon nanowire (SiNW) channels are investigated. Direct observations using thermal images, electrical proof measurements, and supportive numerical simulations are carried out to verify the SHEs. This paper examines the location of hot spots as well as heat dissipation paths (heat sink) depending on the device geometry, and the electrical degradation produced by the SHEs. It also includes the estimation of the surface temperature of the GAA MOSFET and the average temperature across the bulk channel. Design parameters for improved management of the heat dissipation in a device are suggested. This investigation can contribute to improve the device performance and reliability of a 3-D stacked structure.

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

As the current MOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n - or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and subthreshold slopes approaching the thermal limit, ≈ 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.

Electrical characterization of high performance, liquid gated vertically stacked SiNW-based 3D FET biosensors

A 3D vertically stacked silicon nanowire (SiNW) field effect transistor featuring a high density array of fully depleted channels gated by a backgate and one or two symmetrical platinum side-gates through a liquid has been electrically characterized for their implementation into a robust biosensing system. The structures have also been characterized electrically under vacuum when completely surrounded by a thick oxide layer. When fully suspended, the SiNWs may be surrounded by a conformal high-κ gate dielectric (HfO2) or silicon dioxide. The high density array of nanowires (up to 7 or 8×20 SiNWs in the vertical and horizontal direction, respectively) provides for high drive currents (1.3mA/μm, normalized to an average NW diameter of 30nm at VSG=3V, and Vd=50mV, for a standard structure with 7×10 NWs stacked) and high chances of biomolecule interaction and detection. The use of silicon on insulator substrates with a low doped device layer significantly reduces leakage currents for excellent Ion/Ioff ratios >106 of particular importance for low power applications. When the nanowires are submerged in a liquid, they feature a gate all around architecture with improved electrostatics that provides steep subthreshold slopes (SS<75mV/dec), low drain induced barrier lowering (DIBL<20mV/V) and high transconductances (gm>10μS) while allowing for the entire surface area of the nanowire to be available for biomolecule sensing. The fabricated devices have small SiNW diameters (down to dNW∼15–30nm) in order to be fully depleted and provide also high surface to volume ratios for high sensitivities.

The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs

A 3D vertically stacked silicon nanowire (SiNW) and Fin field effect transistor (FET) featuring a high density array (7 or 8×20 SiNWs,>4 Fins vertically stacked) of fully depleted, ultra-thin (SiNWs diameters ∼15–30nm, Fin width/height fw ∼30nm/fh ∼150nm), long (>2μm) and suspended channels has been successfully fabricated for the first time by a top-down, complementary metal oxide semiconductor (CMOS) compatible process on silicon on insulator (SOI) substrates for biosensing applications. SiNW and FinFETs continue to draw interest as biological sensors for their outstanding sensitivity due to their large surface to volume ratios (S/V), high selectivity towards a myriad of analytes through surface functionalization and the possibility for label free, direct monitoring of biological activities. In this paper we describe different strategies and limitations for the successful development and fabrication of a 3D Si nanostructure FET using conventional clean-room fabrication techniques and their integration into heterogeneous systems. The vertical stacking allows for higher utilization of the Si substrate, high output currents (1.3mA/μm, normalized to a NW diameter of 30nm at VSG=3V, and Vd=50mV, for a standard structure with 7×10NWs stacked) and high chances for biomolecule interaction as the number of conduction channels increases. Also, as the NWs/Fins are suspended, their entire surface area is exposed to the sensing analyte. The configuration of the 3D sensor furthermore offers excellent electrostatic control of the channels by the possibility of applying symmetric or asymmetric gate potentials to tune the sensitivity and optimize the power consumption. Our fabrication scheme is competitive in terms of scaling and NW density in comparison to bottom-up and other top-down approaches with the advantage of using a CMOS-compatible, high yield (>90%), reproducible and robust processes.

High-Temperature Performance of Stacked Silicon Nanowires for Thermoelectric Power Generation

Deep reactive-ion etching at cryogenic temperatures (cryo-DRIE) has been used to produce arrays of silicon nanowires (NWs) for thermoelectric (TE) power generation devices. Using cryo-DRIE, we were able to fabricate NWs of large aspect ratios (up to 32) using a photoresist mask. Roughening of the NW sidewalls occurred, which has been recognized as beneficial for low thermal conductivity. Generated NWs, which were 7 μm in length and 220 nm to 270 nm in diameter, were robust enough to be stacked with a bulk silicon chip as a common top contact to the NWs. Mechanical support of the NW array, which can be created by filling the free space between the NWs using silicon oxide or polyimide, was not required. The Seebeck voltage, measured across multiple stacks of up to 16 bulk silicon dies, revealed negligible thermal interface resistance. With stacked silicon NWs, we observed Seebeck voltages that were an order of magnitude higher than those observed for bulk silicon. Degradation of the TE performance of silicon NWs was not observed for temperatures up to 470°C and temperature gradients up to 170 K.

Cross-Section Control of Stacked Nanowires Formed by Bosch Process and Oxidation

The cross-sectional shape of the stacked silicon nanowires (SiNWs) formed by the Bosch process and stress-limited oxidation is studied in this paper. Under the condition of high temperature oxidation, the resulting nanowires highly resemble the initial shapes resulting by the Bosch process. The effects of etching and passivation in the Bosch process are modeled to provide a guideline to control the cross-section of the stacked nanowires.

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fabrication methodology is demonstrated for curved and straight SiNW arrays with different shapes and levels. Ultra-high density SiNW arrays with round or rhombic cross-sections diameters as low as 10 nm are demonstrated for vertical and horizontal spacing of 60 nm. The uniqueness of the technique, which achieves several advantages such as bulk-Si processing, low-thermal budget, and wide process window makes this fabrication method suitable for a very broad range of applications such as nano-electro-mechanical systems (NEMS), nano-electronics and bio-sensing.

Stacked Silicon Nanowires with Improved Field Enhancement Factor

This work describes newly structured stacked silicon nanowires (s-SiNWs), consisting of nanosized silicon wires on top of silicon microrods (SiMRs) and exhibiting pronouncedly superior electron field emission (EFE) characteristics to the conventional SiNWs, by using a two-step electroless metal deposition process. Experimental results indicate that for these s-SiNWs, the electrostatic "screen effect" is markedly suppressed and the field enhancement factor (beta-value) is significantly increased ((beta)(s-SiNWs) = 2533). Additionally, the turn-on field (E(0)) for triggering the EFE process is reduced to a level comparable with that of carbon nanotubes, viz. (E(0))(s-SiNWs) = 2.0 V/mum. This simple and robust modified electroless metal deposition approach does not require either a high temperature or an expensive photolithographic process and possesses great potential for applications.

Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

A simple top-down method for realizing an array of vertically stacked nanowires is presented. The process utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge that is further trimmed to form stacked nanowires by stress-limited oxidation. The process has been demonstrated to be controllable and repeatable, starting with bulk silicon wafers. Vertically stacked gate-all-around MOSFETs have been fabricated, which show excellent performance with a nearly ideal subthreshold slope of 62 mV/dec, a low leakage current, and a high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio of ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> .

Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization

Suspended, stacked and rounded nanowires with diameters as small as 5nm have been obtained thanks to thermal oxidation. Those structures can be used for novel 3D Gate-All-Around Field Effect Transistor (GAAFET) architectures. As the oxidation rate is strongly affected by the nature of the oxidant, the temperature and the wire curvature, both wet and dry oxidations (at 950{degree sign}C and at 1100{degree sign}C, respectively) have been investigated. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) were used to characterize the shape and the oxidation kinetic of the oxidized Si nanowires compared to planar references.

Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization

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