Stability Of Thin-film Transistors Research Articles

Facile routes to enhance doping efficiency using nanocomposite structures for high-mobility and stable PEALD-ITGO TFTs

In–Sn–Ga–O (ITGO) thin-film transistors (TFTs) fabricated by atomic layer deposition (ALD) are promising candidates for widespread semiconductor applications because of their high mobility and stability. To further improve the device characteristics, the doping efficiency of each cation must be increased. Here, we propose a facile method to enhance the device characteristics using plasma-enhanced ALD-nanocomposite (NC) structures. The deposition of SnO2 materials within the In2O3 layer of the ITGO film with the NC-ITO structure accelerates the reduction of In2O3 (In0: 35.3 % →46.1 %), thereby stabilizing SnO2 (Sn4+: 71.0 % →89.1 %). In addition, this process significantly decreases the fraction of oxygen-related defects (Odefect: 24.0 % →17.6 %) because Sn–O has a substantially higher bond dissociation energy than In–O. Consequently, the ITGO TFT with the NC-ITO active layer exhibits considerable improvements in the electrical parameters, such as an increase in the field-effect mobility from 41.9 to 54.5 cm2/V s and an enhancement in the subthreshold swing from 69.8 to 64.8 mV/decade. In addition, the device shows excellent results for negative bias illumination stress and positive bias temperature stress, with the differences in the threshold voltage shift being −0.22 and + 0.06 V, respectively.

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

Selenium-alloyed tellurium oxide for amorphous p-channel transistors.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V-1 s-1 and on/off current ratios of 106-107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

Molecular design direction of organic spacer cations for low-dimensional organic–inorganic hybrid perovskite thin film transistors

Organic spacer cations in low-dimensional organic–inorganic hybrid perovskites (LDPVKs) significantly affect the performance of perovskite materials and devices. Herein, we systematically examine the effects of four distinct organic spacer cations on the properties of materials and perovskite thin film transistors (TFTs). Our study explores the consequences of varying chain lengths, including butylamine (BA) and octylamine (OA), and also considers the impact of incorporating benzene rings, such as phenethylamine (PEA), as well as the influence of fluorine-substituted benzene ring side chains, as represented by fluorine-substituted phenethylamine (FPEA), within these organic spacer cations. The results show that long-chain organic cations such as alkyl-chain cations improve the stability of TFTs but does not improve its field effect mobility. Because it provides π-π stacking, the benzene ring cation improves the carrier mobility performance of LDPVKs. This significantly improves the electrical performance and stability of LDPVK TFTs, affording a field-effect mobility of 7.47 cm2/(V·s) and the threshold voltage difference between the positive and negative sweep (ΔVTH) of 0.25 V. Therefore, when designing provide a molecular design direction for selecting organic spacer cations in low-dimensional for organic–inorganic hybrid perovskites, various factors should be considered to optimized. This work study guides the designing LDPVKs and improving the performances of field-effect devices in the future.

InZnTiON Channel Layer for Highly Stable Thin-Film Transistors and Light-Emitting Transistors.

In this study, we incorporated TiN as a carrier suppressor into an amorphous InZnO channel to achieve stable channels for thin-film transistors (TFTs) and light-emitting transistors (LETs). The low electronegativity and standard electrode potential of the Ti dopant led to a reduction in the number of oxygen vacancies in the InZnO channel. Moreover, the substitution of nitrogen into the oxygen sites of InZnO effectively decreased the excess electrons. As a result, the cosputtering of the TiN dopant resulted in a decrease in the carrier concentration of the InZnO channel, serving as an effective carrier suppressor. Due to the distinct structures of TiN and InZnO, the TiN-doped InZnO channel exhibited a completely amorphous structure and a featureless surface morphology. The presence of oxygen vacancies in the InZnO channel creates trap states for electrons and holes. Consequently, the TFT with the InZnTiON channel demonstrated an improved subthreshold swing and enhanced stability during the gate bias stress test. Furthermore, the threshold voltage shift (ΔVth) changed from 3.29 to 0.86 V in the positive bias stress test and from -0.92 to -0.09 V in the negative bias stress test. Additionally, we employed an InZnTiON channel in LETs as a substitute for organic semiconductors. The reduction in the number of oxygen vacancies effectively prevented exciton quenching caused by hole traps within the vacancies. Consequently, appropriate TiN doping in the InZnO channel enhanced the intensity of the LET devices.

Theoretical Modeling of a Temperature-Dependent Threshold-Voltage Shift in Self-Aligned Coplanar IZTO Thin-Film Transistors

Here, we investigate the effect of increasing temperature on threshold voltage (VTH) stability in self-aligned coplanar amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs). An analytical model of the temperature dependency of VTH stability reveals the importance of device geometry and subgap density-of-state (DOS) reductions in highly stable a-IZTO TFTs. The validity of the analytical model is confirmed using experiments and technology computer-aided design simulations to predict quantitative relationships under various shifts in temperatures, subgap DOS, and VTH. The role of hydrogen impurity in performance and VTH stability is also examined. The incorporation of hydrogen in a-IZTO channels improves TFT performance and thermal stability (ΔVTH/ΔT = 3.18 mV/K) due to hydrogen’s role as a passivation center. However, excessive incorporation of hydrogen increases subgap DOS distribution, causing a slight deterioration in thermal stability (ΔVTH/ΔT = 3.31 mV/K). This suggests that hydrogen can be converted from a shallow donor to an acceptor-like deep trap state. Our findings inform future designs of stable oxide semiconductor TFTs in terms of thermal stability in emerging organic light-emitting diode, augmented and virtual reality, memory, logic, and monolithic three-dimensional applications.

Optimal Aluminum Doping Method in PEALD for Designing Outstandingly Stable InAlZnO TFT

AbstractOxide semiconductors are promising semiconducting materials for next‐generation thin‐film transistors (TFTs). The role of the cations should be considered in the design of oxide semiconductors suitable for various applications. Ga has been widely used as a carrier suppressor in oxide semiconductors; however, research has recently been conducted to replace it with Al, which is cheaper and forms a stronger bond with O. Deposition using plasma‐enhanced atomic layer deposition (PEALD) is very useful for controlling the composition of the cations in an oxide semiconductor. In this study, an InAlZnO (IAZO) semiconductor was deposited using super‐cycle PEALD for the first time. Al2O3 (AO), AlZnO (AZO), and InAlO (IAO) as Al doping layers in IAZO are evaluated. Considering its electrical characteristics and stability, AZO is selected as the optimal Al doping layer. The IAZO thin film and TFT characteristics according to the Al doping method are examined through the role of the cations and H concentration. In addition, the Al concentration is controlled by adjusting the number of cycles in super‐cycle PEALD. As the Al concentration decreased, the mobility increased; however, the stability degraded significantly, which is induced by the increase in oxygen vacancies. Finally, the high‐Al IAZO system using AZO successfully showed overall excellent properties including mobility over 10 cm2 V−1 s, and outstanding stability under 0.1 V, which are greatly improved compared to previously reported IAZO TFTs.

Solution-processed high stability top-gate W and F co-doped ZnSnO thin film transistors

In this work, top-gate structured W: F co-doped Zn–Sn–O (ZTO) thin-film transistors (TFTs) with excellent stability are prepared by the solution process. Comparing with the undoped ZTO TFT, the mobility of W: F co-doped ZTO TFTs was up from 1.87 to 3.14 cm2 V−1 s−1, and the subthreshold swing decreases from 0.192 to 0.157 V/dec. Moreover, the W: F co-doped ZTO TFTs exhibit a small Vth shift of −0.09 V under negative bias illumination stress, which is close to one of the TFTs prepared by the traditional vacuum process. X-ray photoelectron spectroscopy and capacitance–voltage examination revealed that the enhanced stability is due to the fact that W: F co-doping can effectively suppress defect states in ZTO films. The results manifest that W: F co-doping may be a promising method for enhancing the stability of TFTs with the top-gate structure.

A Comparative Study on Self‐Aligned Top‐Gate Thin‐Film Transistors with Silicon Nitride as the Interlayer

Thin-film transistors (TFTs) with self-aligned top-gate structure are fabricated, in which the source/drain region is pretreated to be highly conductive during the deposition of silicon nitride as the interlayer. Without deteriorating the properties of the device's channel layer, the basic performance of TFTs can be simply controlled by altering the SiH4 flow rate during the deposition of silicon nitride film. Furthermore, the diffusion of hydrogen dissociated from SiH4 precursor, which can passivate the electron traps at the interface between the channel and dielectric layer or in the bulk of the dielectric layer, can significantly improve the positive bias temperature stress stability. The charge trapping mechanism is verified using the stretched-exponential model, and the rising values of the fitting parameters (ΔVth0 and τ) show that the TFTs stability improves as the flow rate of SiH4 rises. This approach can reduce the cost and simplify the manufacturing of thin-film transistors.

Enhanced electrical stability of thin film transistors based on nanocrystalline silicon films

In this work, nanocrystalline silicon (nc-Si) films were achieved by using normally processing method of amorphous silica thin film transistors (a-Si TFTs), plasma enhanced chemical vapor deposition (PECVD). The effects of PECVD process parameters on the crystallization rate of nc-Si films were comprehensively studied and then an optimized nc-Si film has been achieved with a crystallinity of 50.87%. The electrical properties and stability of nc-Si TFTs are further investigated and compared with a-Si TFTs. The ΔV th of the nc-Si TFTs are 0.14 V and −3.32 V under positive bias-temperature-illumination stress (60 °C, 30 V, 6000 nit) and negative bias-temperature-illumination stress (60 °C, −30 V, 6000 nit) after 1 h, which are 1.96 V and −5.51 V for a-Si TFT, respectively. The result reveals better photo stability of nc-Si TFTs than a-Si TFTs which is attributed to fewer defect states in nc-Si films.

Impact of layer thickness on the operating characteristics of In2O3/ZnO heterojunction thin-film transistors

Combining low-dimensional layers of dissimilar metal oxide materials to form a heterojunction structure offers a potent strategy to improve the performance and stability of thin-film transistors (TFTs). Here, we study the impact of channel layer thicknesses on the operating characteristics of In2O3/ZnO heterojunction TFTs prepared via sputtering. The conduction band offset present at the In2O3/ZnO heterointerface affects the device's operating characteristics, as is the thickness of the individual oxide layers. The latter is investigated using a variety of experimental and computational modeling techniques. An average field-effect mobility (μFE) of >50 cm2 V−1 s−1, accompanied by a low threshold voltage and a high on/off ratio (∼108), is achieved using an optimal channel configuration. The high μFE in these TFTs is found to correlate with the presence of a quasi-two-dimensional electron gas at the In2O3/ZnO interface. This work provides important insight into the operating principles of heterojunction metal oxide TFTs, which can aid further developments.

Effect of Humidity on Properties of Aqueous-Processed Tb-Doped Indium Oxide Thin-Film Transistors

Aqueous route is readily for fabricating oxide thin-film transistors (TFTs), but the relative humidity (RH) impacts evolution of oxide thin films. Herein, the effect of RH on the electronic performance and bias stability of aqueous-processed Tb-doped indium oxide (Tb:In2O3) TFTs is investigated. The mobility is sensitive to RH. By tuning the RH for desirable thickness and density of the obtained Tb:In2O3 films, the TFTs present optimized mobility of 13.0 cm2/Vs, with high ON/OFF ratio of 108. Notably, low threshold voltage shift of −0.35 V and 0.42 V under negative and positive gate bias stress are simultaneously obtained with a fabricating RH of 40%. Moreover, dry ambience (RH <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le23$ </tex-math></inline-formula> %) affords to abundant nanopores and defects, resulting in inferior performance and stability of the aqueous-processed oxide TFTs. And high humid ambience easily ruins the uniform of precursor films. This work indicates the strategy to fabricate highly stable oxide TFTs with high performance.

(Invited) Approach to Oxide Tfts with High Mobility & Stability

Thin film transistors (TFTs) with the channel of amorphous oxide semiconductors (AOSs) represented by amorphous Indium-Gallium-Zinc Oxide (a-IGZO) are now applied to drive pixels of the state-of the art display based on high mobility, good homogeneity, easy fabrication and optical transparency [1]. Recently, larger mobility TFTs are highly demanded for emerging applications such as ultra-high vision and memories. However, there is a critical obstacle to be overcome, i.e., an empirical trade-off rule in oxide TFTs between mobility and stability. Higher mobility TFTs possess less stability to various types of stress (negative bias-thermal stress instability, NBTS, positive bias-thermal stress instability, PBTS, and negative bias-illumination stress instability, NBIS). The Elucidation of origin for this trade-off rule and new approach are required to realize high mobility and high stability TFTs. We clarify that the origin of this trade-off through comparison in TFTs between IGZO with low mobility and high stability and ITZO with high mobility and low stability. A critical phenomenon was noted during the conventional TFT fabrication; CO-related impurity donates electrons to Indium-Tin-Zinc Oxide (ITZO) with high mobility under the negative bias stress condition but such CO-related impurity effect is negligible in IGZO with lower mobility than ITZO [2]. This finding may be understood by considering that large difference in ECBM determines the transfer of electron generated by adsorbed CO-related species on the back surface of ITZO [3]. Based on this model and this finding, we successfully fabricated the most stable ITZO TFT with a high mobility of 70 cm2/Vs by eliminating CO-related impurity and further passivation; NBTS (-20V, 60 oC, 3600 s, ΔVth: -0.02 V), PBTS (+20 V, 60 oC, 3600 s, ΔVth: 0.12 V) and NBIS (-20V, 15000 lx, 3600s, ΔVth: -1.33 V).[1] Hosono, H., & Kumomi,K., (ed), Amorphous Oxide Semiconductors: IGZO and Related Materials for Display and Memory (Wiley, 2022); Hosono, H. (2018). How we made the IGZO transistor. Nature Electronics, 1(7), 428-428.[2]Shiah, Y. S., Sim, K., Ueda, S., Kim, J., & Hosono, H. (2021). Unintended Carbon-Related Impurity and Negative Bias Instability in High-Mobility Oxide TFTs. IEEE Electron Device Letters, 42(9), 1319-1322.[3] Shiah, Y. S., Sim, K., Shi, Y., Abe, K., Ueda, S., Sasase, M., Kim,J., & Hosono, H. (2021). Mobility–stability trade-off in oxide thin-film transistors. Nature Electronics, 4(11), 800-807.

Significant performance and stability improvement of low-voltage InZnO thin-film transistors by slight La doping

Low-voltage, solution-processed oxide thin-film transistors (TFTs) have shown great potential in next-generation low-power, printable electronics. However, it is now still quite challenging to obtain low-voltage oxide TFTs with both high mobility and stability, especially for solution-processed ones. In this work, La-doped InZnO (IZO:La) channel for high performance and stable TFTs is developed using a simple solution process. The effects of La composition in IZO:La on the film and TFT performance are systematically investigated. It is confirmed that the incorporation of appropriate La could control the carrier concentration, improve the surface morphology, and passivate the oxygen-related defects, leading to a reduced trap density both at dielectric/channel interface and within the channel layer. As a result, the optimized TFTs with 1% La dopants exhibit the best overall performance, including a low operating voltage of 1 V, a high mobility of 14.5 cm2/V s, a low subthreshold swing of 109 mV/dec, a turn-on voltage close to 0 V, and negligible changes of performance under both positive and negative bias stresses. This work might support the development of all-solution-processed oxide TFT backplanes for battery-powered active-matrix displays.

(Invited) Oxide Electronics and Recent Progress in Bipolar Applications

The discovery of oxide electronics is of increasing importance today as one of the most promising new technologies and manufacturing processes for a variety of electronic and optoelectronic applications such as next-generation displays, batteries, solar cells, memory devices, and photodetectors[1]. The high potential use seen in oxide electronics is due primarily to their high carrier mobilities and their ability to be fabricated at low temperatures[2]. However, since the majority of oxide semiconductors are n-type oxides, current applications are limited to unipolar devices, eventually developing oxide-based bipolar devices such as p-n diodes and complementary metal-oxide semiconductors.We have contributed to a wide range of oxide semiconductors and their electronics and optoelectronic device applications. Particularly, we have demonstrated n-type oxide-based thin film transistors (TFT), integrating In2O3-based n-type oxide semiconductors from binary cation materials to ternary cation species including InZnO, InGaZnO (IGZO), and InAlZnO. We have suggested channel/metallization contact strategies to achieve stable and high TFT performance[3, 4], identified vacancy-based native defect doping mechanisms[5], suggested interfacial buffer layers to promote charge injection capability[6], and established the role of third cation species on the carrier generation and carrier transport[7]. More recently, we have reported facile manufacturing of p-type SnOx through reactive magnetron sputtering from a Sn metal target[8]. The fabricated p-SnOx was found to be devoid of metallic phase of Sn from x-ray photoelectron spectroscopy and demonstrated stable performance in a fully oxide-based p-n heterojunction together with n-InGaZnO. The oxide-based p-n junctions exhibited a high rectification ratio greater than 103 at ±3 V, a low saturation current of ~2x10-10, and a small turn-on voltage of -0.5 V.In this presentation, we review recent achievements and still remaining issues in transition metal oxide semiconductors and their device applications, in particular, bipolar applications including p-n heterostructures and complementary metal-oxide-semiconductor devices as well as single polarity devices such as TFTs and memristors. In addition, the fundamental mechanisms of carrier transport behaviors and doping mechanisms that govern the performance of these oxide-based devices will also be discussed.ACKNOWLEDGMENTThis work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education.REFERENCES[1] K. Nomura et al., Nature, vol. 432, no. 7016, pp. 488-492, Nov 25 2004.[2] D. C. Paine et al., Thin Solid Films, vol. 516, no. 17, pp. 5894-5898, Jul 1 2008.[3] S. Lee et al., Journal of Applied Physics, vol. 109, no. 6, p. 063702, Mar 15 2011, Art. no. 063702.[4] S. Lee et al., Applied Physics Letters, vol. 104, no. 25, p. 252103, 2014.[5] S. Lee et al., Applied Physics Letters, vol. 102, no. 5, p. 052101, Feb 4 2013, Art. no. 052101.[6] M. Liu et al., ACS Applied Electronic Materials, vol. 3, no. 6, pp. 2703-2711, 2021/06/22 2021.[7] A. Reed et al., Journal of Materials Chemistry C, 10.1039/D0TC02655G vol. 8, no. 39, pp. 13798-13810, 2020.[8] D. H. Lee et al., ACS Applied Materials & Interfaces, vol. 13, no. 46, pp. 55676-55686, 2021/11/24 2021.

Gold Nanoparticle-Crystalline rubrene hybrid nanocomposite via plasma processing and realization of Plasmon-enhanced organic thin film transistor with high responsivity

High performing and operationally stable thin film transistor device is successfully fabricated with an organic frame-work implemented by synthesis of rubrene crystals with gold nanoparticles (Au NPs). A novel synthesis route for the fabrication of the active material in the form of crystalline rubrene composite (CRC) is adopted via plasma processing approach. This report highlights two important features: a) report of a one-step process to synthesize crystalline rubrene gold nanocomposite in a thin film architecture and b) demonstration of a plasmon transistor for plasmon resonance energy detection. The fabricated device is a low-light responsive device showing the typical p-type characteristics. Excellent p-channel characteristics is shown by the device with a maximum field effect mobility of 0.215 cm2/V.s. At the peak wavelength of plasmonic absorption a very high responsivity of 25 A/W is achieved. Hot carriers are collected by the transistor from the nanostructures of Au NPs that contributes to the increase in drain current by modulating the channel conductivity. Due to the versatile nature of the plasmonic nanostructures in terms of wavelength tunability for the CRC material, this architecture has the potential to offer a wide range of spectrum that can be used in various applications.

Combination of InZnO/InGaZnO Bi-layered channels prepared by atomic layer deposition and ozone-based gate-stack formation for guaranteeing high field-effect mobility and long-term stability of thin film transistors

Bi-layered channel structures comprising In–Zn–O (IZO) prompt and In–Ga–Zn-O (IGZO) prime layers were introduced to enhance the carrier mobility of oxide thin film transistors (TFTs) by atomic layer deposition (ALD) technique. Considering that hydrogen-related species in the gate stack may convert the semiconducting channel with In-rich composition into a more conducting layer during the ALD process, ozone oxidant was chosen for the formation of Al2O3 protection and gate insulator layers. The TFT using a IZO/IGZO bi-layered channel exhibited the highest carrier mobility of 50.8 cm2/Vs when the film thickness and ALD sub-cyclic ratio between the In and Zn precursors for the IZO prompt layer were designed to be 3 nm and 2:1, respectively. The optimum cationic compositions of the IZO and IGZO layers were determined to be 1.3:1 (In:Zn) and 1.4:1:2 (In:Ga:Zn), respectively. The turn-on position of the fabricated device was located at near 0 V without additional heat treatment. Furthermore, the device using the optimum IZO/IGZO bi-layered channel exhibited threshold voltage shifts (ΔVTH) of +1.8 V under a positive bias stress (PBS) condition that corresponded to an improvement over a single IGZO channel device (+4.5 V). From the numerical analyses on the sub-gap states below the conduction band edge and trap densities in the mid-gap regions, it was found that the electron trapping sites especially located in deep-level states could be reduced by implementing a bilayer channel configuration. Alternatively, the ΔVTH further decreased to +1.3 V during the PBS at an elevated temperature of 80 °C because of the migration of hydrogen from the gate stack toward the active channel during the measurement, demonstrating the synergic impact of bi-layered channel structures and gate-stack formation conditions.

Comparative Study of Atomic Layer Deposited Indium-Based Oxide Transistors with a Fermi Energy Level-Engineered Heterojunction Structure Channel through a Cation Combinatorial Approach.

Amorphous indium-gallium-zinc oxide (a-IGZO) has become a standard channel ingredient of switching/driving transistors in active-matrix organic light-emitting diode (AMOLED) televisions. However, mobile AMOLED displays with a high pixel density (≥500 pixels per inch) and good form factor do not often employ a-IGZO transistors due to their modest mobility (10-20 cm2/(V s)). Hybrid low-temperature polycrystalline silicon and oxide transistor (LTPO) technology is being adapted in high-end mobile AMOLED devices due to its ultralow power consumption and excellent current drivability. The critical issues of LTPO (including a complicated structure and high fabrication costs) require a search for alternative all-oxide thin-film transistors (TFTs) with low-cost processability and simple device architecture. The atomic layer deposition (ALD) method is a promising route for high-performance all-oxide TFTs due to its unique features, such as in situ cation composition tailoring ability, precise nanoscale thickness controllability, and excellent step coverage. Here, we report an in-depth comparative investigation of TFTs with indium-gallium oxide (IGO)/gallium-zinc oxide (GZO) and indium-zinc oxide (IZO)/GZO heterojunction stacks using an ALD method. IGO and IZO layers with different compositions were tested as a confinement layer (CL), whereas the GZO layer was used as a barrier layer (BL). Optimal IGO/GZO and IZO/GZO channels were carefully designed on the basis of their energy band properties, where the formation of a quasi-two-dimensional electron gas (q2DEG) near the CL/BL interface is realized by rational design of the band gaps and work-functions of the IGO, IZO, and GZO thin films. To verify the effect of q2DEG formation, the device performances and stabilities of TFTs with CL/BL oxide heterojunction stacks were examined and compared to those of TFTs with a single CL layer. The optimized device with the In0.75Zn0.25O/Ga0.80Zn0.20O stack showed remarkable electrical performance: μFE of 76.7 ± 0.51 cm2/(V s), VTH of -0.37 ± 0.19 V, SS of 0.13 ± 0.01 V/dec, and ION/OFF of 2.5 × 1010 with low operation voltage range of ≥2 V and excellent stabilities (ΔVTH of +0.35, -0.67, and +0.08 V for PBTS, NBIS, and CCS, respectively). This study suggests the feasibility of using high-performance ALD-derived oxide TFTs (which can compete with the performance of LTPO transistors) for high-end mobile AMOLED displays.

High Mobility and Photo‐Bias Stable Metal Oxide Thin‐Film Transistors Engineered by Gradient Doping

AbstractDoping of oxygen‐deficient binder is an efficient way to alleviate the photo‐bias instability issue of oxide thin‐film transistors (TFTs). However, almost all dopants are working as electron suppressors and degrading mobility. Here we report an effective three‐level O‐anti|O|O‐N (OI|OII|N) gradient doping solution to overcome the adverse mobility‐stability trade‐off in N‐doped InGaZnO (IGZO:N) TFTs. 100 nm‐thick IGZO:OI|IGZO:OII|IGZO:N (IGZO:OI|OII|N) junctionless channel layers are fabricated by varying the partial pressures of oxygen and nitrogen doping gases. Best balance between improved performance and negligible degraded stability is first engineered by reducing the back‐channel IGZO:N depth close to the theoretical diffusion length of photo‐excited holes and forming two‐level graded IGZO:OII|N (40 nm|60 nm) TFTs. Much improved performance and comparable stability are further induced by incorporating ~1.5 nm percolation conduct IGZO:OI at the front‐channel to enhance accumulation. The three‐level graded IGZO:OI|OII|N TFTs exhibit high mobility (34.25 cm2 V−1 s−1) and good photo‐bias stability (∆Vth = −0.85 V@10 000 cd m−2, 3.0 h), which are 2~5‐fold superior to those of the controlled two‐level graded IGZO:OI|N TFTs, IGZO:OII|N TFTs, and homogeneous IGZO:OII TFTs, IGZO:N TFTs. The fabrication of high mobility and photo‐bias stable IGZO TFTs paves the way to future high‐performance oxide electronics.

Low doping in-situ strategy leading to polysilicon based TFTs exhibiting high stability under stress effects and enhanced electrical performances

In the present work, we investigate the effect of low phosphorus doped polysilicon thin films. These later are deposited on glass substrates by low pressure chemical vapor Deposition (LPCVD) technique and are in situ doped with phosphine adjunction to silane. Doping levels are reported by the phosphine to silane ratio Γ varying from 0 (undoped layer) to heavily doped layer almost 1.2 × 10–3. Films are characterized by different techniques as Photothermal Deflection Spectroscopy (PDS), photoluminescence measurements and x-ray diffraction of polycrystalline layers. The last one reveals that doping concentration giving modification in crystallite size and presence of microstrain, so a clear reduction in the Eg value was observed for the slightest doped layer (Γ = 3.7 × 10–7) by comparaison with the undoped one ((Γ = 0). Results give evidence of an optimum doping level to obtain higher polysilicon films quality. Polysilicon film quality has been correlated to phosphorus doping levels. Thin film transistors (TFTs) are fabricated on glass substrate using a top gate four mask process at low temperature (<600 °C). Electrical characterizations highlight significant improvements in the TFTs performances using slightly doped film instead of undoped one as active layer. Based on Levinson’s model, density of states within the grain boundaries is also found to be the lowest. Stability under stress is enhanced too. For slightly doped films, electrical characterizations indicate that both threshold voltage and density of states NT within the grain boundaries have their lowest values. Although, the field effect mobility μ records its highest values. Additionally, low doping levels enhances the TFT stability under stress. As a result, the in situ low doping strategy opens the way to manufacture polysilicon electronic devices exhibiting high electrical performances and a rather high stability under stress effects.