SRAM Circuit Research Articles

Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization

Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization

A High-Precision Voltage-Quantization-Based Current-Mode Computing-in-Memory SRAM.

Non-linear distortion of signals is a serious problem in computing-in-memory SRAM (CIM-SRAM) circuits in current mode. This problem greatly limits the performance of calculations and directly affects the computing power of the CIM-SRAM. In this study, the causes of non-linearity and inconsistency were investigated. Based on detailed analyses, we proposed a high-precision, fully dynamic range IV (HFIV) conversion circuit. The HFIV circuit was added to each bit line (BL) for voltage clamping and proportionally mirroring the read current. We applied the structure to numerous prior studies and evaluated them using the 55 nm complementary metal-oxide semiconductor process. The results showed the proposed HFIV circuit could increase the CIM-SRAM's calculation linearity to 99.92% (8~32 SRAM bit-cells) and 99.8% (32~64 SRAM bit-cells) with a 1.2 V supply.

Composite Gate Oxide Method for Improving the Reliability and Leakage Performance of Deep Submicron CMOS Processes

This article aims to address the issues of gate oxide reliability failure and leakage loss in SRAM circuits caused by the introduction of additional high-voltage devices in the 90 nm standard process. It investigates the corner thinning phenomenon using different gate oxide scheme. It analyzes the corresponding relationship between composite gate oxide and reliability and tests the leakage of the SRAM circuit. Research has shown that the use of composite gate oxide can effectively improve corner thinning. The ratio of thermal oxide to HTO in composite gate oxide directly affects GOI/TDDB. At the same time, the use of composite gate oxide also decreases device leakage to a certain extent. The standby leakage of SRAM circuits(Isb) can be reduced from 200 nA to less than 10 nA.

Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications.

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect.

In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit's upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection.

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K

In this work, we are the first to investigate and model the characteristics of a commercial 5nm FinFET technology from room temperature (300K) all the way down to cryogenic temperature (10K). We focus on SRAM circuits demonstrating how cryogenic temperatures impact their power, delay, and reliability. SRAM memories are key components in quantum read-out and control circuits, and therefore characterizing their key figure of merits when building cryogenic-CMOS circuits is essential. To achieve that, we first measure the electrical characteristics of nFinFET and pFinFET devices from 300K down to 10K. Then, we carefully calibrate the cryogenic-aware BSIM-CMG, which is the first industry-standard compact model for FinFET technologies designed for cryogenic temperatures. This enables us to reproduce the experimental data in which SPICE simulations come with an excellent agreement with the measurements. Using our well-calibrated transistor models, we simulate a complete 32-bit SRAM memory array, including a write driver, sense amplifier, pre-charger, and output latch. Then, we investigate how cryogenic temperatures impact the SRAM read and write delays at several stages during the operation, as well as the power and energy. For a more comprehensive analysis, we perform our studies for different SRAM types covering high-density, high-performance, and low-voltage cells. All transistor and SRAM analyses are performed at both room temperature and cryogenic temperature to obtain detailed comparisons revealing the exact role that cryogenic temperature plays in SRAMs. All in all, we demonstrate that commercial 5nm FinFET is indeed suitable for cryogenic-CMOS circuits required in quantum processors, revealing that the performance of SRAMs at 10K does improve while power and energy consumption are reduced. Nevertheless, SRAM reliability is more challenging in which noise margins need to be carefully engineered to remain sufficient at 10K.

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node.

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit

Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit

Design and Analysis of SRAM Cell for Smart Application

In today's circuittechnology, power consumption and savings are key concerns. The driving reasonsbehind these innovations are portable devices that require high throughput andlow power dissipation, such as computers, phones, and Personal DigitalAssistants (PDAs). In portable devices, reducing or decreasing IC dissipatedpower through design optimization is a big problem, and restricted batterylifespan places very severe restrictions on overall power usage. In this study SRAMcircuit for smart applications has been investigated using various factors suchas write, read, dynamic, static power with voltage and temperature. The powerconsumption analysis is the most essential criteria for memory design. Becausedata stability is a critical concern, affecting both the read and write operations.The implemented 9T SRAM in this study is more efficient than the other SRAM interms of power usage. When compared with the existing SRAM circuits taken forcomparison of different parameters, the proposed 9T SRAM, circuit uses lessthan 28.2% write power, while it uses about the same for read operation. Thedata retention voltage for both circuits is 0.29 V, which is utilized to storethe data in the circuit. The 32 nm Bulk CMOS process technology from PTM filesis used for designing and analysis.

Simulation-Based Recommendations for Digital Circuits Design Using Schottky-Barrier-Type GNRFET

The use of graphene nano-ribbon field-effect transistors (GNRFETs) in the nanoscale circuits design is challenging because there are several adjustable parameters that need to be selected carefully. In this paper, we evaluate the impact of changes in different GNRFETs’ parameters including channel length (Lch), oxide thickness (Tox), line-edge roughness (Pr), number of dimer lines (N), supply voltage, and temperature on the performance of inverter, Flip-Flop, and SRAM circuits. Performance analysis in terms of noise margin (NM), delay, average power, and energy-delay-product (EDP) show that those adjustable parameters of the GNRFETs are of a significant role in attaining low-power or high-performance requirements. To achieve low-power designs, GNRFETs with perfectly smooth edges and higher Tox should be used. For low-power designs with a smaller oxide thickness, it is suggested to select 9 for N with very low Pr. Otherwise, the priority would be choosing 13 for N. To attain high-performance designs with low delay, it is recommended to use the GNRFETs without Pr. If the edges of graphene nano-ribbons are not smooth, choosing (3p+1, ) periodic for N provides a potential improvement in circuit delay. Moreover, selecting 18 for N and smaller Tox provides a potential improvement in circuit delay.

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

Brain-Inspired Computing for Circuit Reliability Characterization

Transistor scaling steadily approaches fundamental limits. Sustaining circuit reliability becomes an overwhelming challenge for foundries. Therefore, early and rapid characterization of degradation effects impacting the circuits transistors becomes essential. Such degradation effects are caused by design-time variation due to manufacturing variability and/or run-time variation due to transistor aging. In this work, we are the first to employ Brain-Inspired Hyperdimensional computing (HDC) for circuit reliability. HDC is an emerging light-weight machine-learning solution. Nowadays, it is mainly applied to bio-signal processing. We bring the research of HDC to the next level by demonstrating how it can be applied to address the challenges in circuit reliability. This has far-reaching consequences due to the large savings achieved by 1) reducing the amount of training data, 2) removing the need to send the data to the Cloud for model training, and 3) significantly speeding up the characterization and classification tasks. We demonstrate the viability of HDC, using SRAM and other circuits as an example. HDC outperforms traditional machine learning methods, such as support vector machine, in accuracy and requires up to 20x fewer training samples. Our implementation and analysis are based on industrial 14 nm FinFET fully calibrated with Intel measurements.

An Accurate Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization

In sub-10nm FinFETs, Line-edge-roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variability (PIV) aware compact model-based circuit performance estimation for Design-Technology Co-optimization (DTCO). This work is carried out using an experimentally validated BSIM-CMG model on a 7nm FinFET node. First, we have shown performance bench-marking of LER and MGG models with the state-of-the-art and shown {\textbackslash}4x({\textbackslash}2.3x) accuracy improvement for NMOS(PMOS) in the estimation of device figure of merits (DFoMs). Second, RO and SRAM circuits performance estimation is carried out for LER and MGG variability. Further, {\textbackslash}22\% more optimistic estimate of ({\sigma}/{\mu})\textsubscript{SHM} (Static Hold Margin) compared to the state-of-the-art model with V\textsubscript{DD} variation is shown. Finally, we demonstrate our improved DFoMs accuracy translated to more accurate circuits figure of merits (CFoMs) performance estimation. For worst-case SHM (3({\sigma}/{\mu})\textsubscript{SHM}@VDD=0.75 V) compared to state-of-the-art, dynamic(standby) power reduction by {\textbackslash}73\%({\textbackslash}61\%) is shown. Thus, our enhanced variability model accuracy enables more credible DTCO with significantly better performance estimates.

Design of low delay 4X4 SRAM memory using quantum dot cellular automation technology

Nanotechnology is concerned with materials, structures and systems whose components exhibit new and changing physical, chemical and biological properties as a result of their nanoscale sizes. It is a new technology used to design logic circuits with small size, low energy consumption and high frequency (of the order of Tera Hertz).and it is the leading candidate for the nanotechnology to replace the CMOS technologies that is used in manufacturing of the most today's electronic devices. In this research we have designed a low-delayed 4X4 SRAM circuit using the previous technology, The simulation results showed that the proposed design performs the required logic function with a delay that is about a third lower for the reading process and about a half for the writing process compared with the best previous designs of the same size or which allows reading/writing the same number of bits from/to memory.

Characterization of Stable 12T SRAM with Improved Critical Charge

With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces the conventional inverter with Schmitt trigger-based inverter in core latch. The proposed SRAM circuit has been compared with four formerly reported designs for investigating the improvement in terms of various performance metrics. These designs include conventional six transistors (6T), tunable transistor 8T (T8T), PPN inverter-based 10T (PP10T), and stable low read power 11T (S11T) cells. The presented cell effectively minimizes the soft errors attributed to [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text] enhancement of critical charge compared to 6T/T8T/PP10T/S11T cells. Also, the proposed bit-cell effectively mitigates multi-bit-cell upsets because it allows bit interleaving array structure. The presented bit-cell also shows reduction in leakage power by [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text] in comparison to 6T/T8T/PP10T/S11T cells, respectively. The read and write stability of proposed bit-cell circuit is enhanced by [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text]/[Formula: see text]/[Formula: see text], respectively, in comparison to 6T/T8T/PP10T/S11T cells, respectively. In addition to this, proposed cell exhibits improvement in dynamic power, data retention voltage, and overall electrical quality matrix. Variability comparison of key design metrics such as read power and read current of the proposed SRAM circuit with 6T cell has also been presented in this work.

Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

This paper proposes the analytical surface potential and threshold-voltage model for performance investigation of gate stack (GS) dual-metal-insulated-gate (DMIG) source-engineered (SE) Fully-depleted silicon-on-insulator (FD SOI) MOSFET for low-power digital applications. In which, a new concept of dielectric-modulated high-k insulator-gap with source engineering has been analytically formulated for the first time in dual-metal-gate technology-based FD SOI MOSFET. The surface potential model is developed using two-dimensional Poisson's equations with including effects of interface trap charges (ITCs) and verified against numerical simulations over the TCAD tool from Silvaco ATLAS™. Also, the parametric analysis has been performed to optimize the device dimensions for better nanoscaled MOS design. Further, a six transistor (6-T) SRAM cell is designed using n/p-GS-DMIG SE FD SOI MOSFET for the analysis of static-noise-margin (SNM). It is observed that the proposed FD SOI MOSFET offers excellent immunity towards short-channel-effects (SCEs) along with improved SRAM circuit performance at different ITC conditions. • Impact of interface Trap Charges (ITCs) on GS-DMIG SE FD SOI MOSFET. • Analytical Modeling of Surface Potential and Threshold Voltage of GS-DMIG SE FD SOI MOSFET. • Analysis of DIBL effect at different ITC Conditions. • Comparative analysis of proposed FD SOI MOSFET in nanoscale regime. • Design and Analysis of 6T-SRAM cell using n-/p-GS-DMIG SE FD SOI with including effects of ITCs.

A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between VDD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply VDD and ground in all the possible ternary logic states.While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.

Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

AbstractWe present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications.