Square Root Carry Select Adder Research Articles

Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique

Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture

An energy and area efficient yet high-speed square-root carry select adder structure

In this paper, we propose a modified carry select adder (CSLA) structure which is more power/energy and area-efficient compared to the existing CSLAs. The higher efficiency is achieved by modifying the logic formulations of the carry generation and selection (CGS) scheme and merging all of its redundant logic operations in the carry generation (CG) and carry selection (CS) units of the CGS-based CSLA (CGS-CSLA) structure. This leads to a simplified structure. Next, the proposed CSLA structure is employed to design efficient square-root CSLA (SQRT-CSLA) structure. The efficiency of the proposed SQRT-CSLA is investigated by comparing its speed, power, energy, and area parameters with those of some other SQRT-CSLA structures, including conventional SQRT-CSLA, binary to excess-1 converter, common Boolean logic, and the CGS-based SQRT-CSLA structures. The investigation, which is performed using HSPICE simulations based on a 45nm bulk CMOS technology, includes 8, 16, 32, and 64-bit adder structures. The impact of voltage scaling on the efficiency of the proposed structure is also studied by changing the supply voltage levels from the near-threshold voltage to the nominal supply voltage. Simulation results reveal that the proposed SQRT-CSLA provides, at least, 14%, 14%, and 15% lower energy, energy-delay product, and area-delay product, respectively, compared to those of the CGS-based SQRT-CSLA structure, averaged over the supply voltage and bit length.

VHDL Implementation of Fast Multiplier based on Vedic Mathematic using Modified Square Root Carry Select Adder

this paper, a novel technique for multiplication is presented using Vedic multiplier. Vedic multiplier uses adders and hence making fast adder will increase the overall speed for multiplication. We have done comparative analysis for multiplication using different architectures of adder. For comparison we have taken Carry Select Adder (CSA), Square Root Carry Select Adder (SQRT-CSA). We have proposed Vedic multiplication using Modified SQRT-CSA. VHDL design in proposed and synthesis is performed on Virtex-4 FPGA.

Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder

In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based on this modification a new modified 32-Bit Square-root CSLA (SQRT CSLA) architecture has been developed. The modified architecture has been developed using Common Boolean Logic(CBL). The proposed architecture has reduced area, power and delay.

A DESIGN OF AREA AND POWER EFFICIENT HIGH SPEED DATA PATH LOGIC SYSTEM

Carry Select Adder (CSLA) is one of the fastest adders use in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Implementing Design of Modified Area Efficient Enhanced Square Root Carry Select Adder

In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In following paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) is proposed. Based on this modification a new architecture has been developed and compared with the regular and modified Square-root CSLA (SQRT CSLA) architecture. The modified architecture has been developed using Binary to Excess-1 converter (BEC). The proposed work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in CMOS process technology. The proposed architecture has reduced area, power and delay as compared with the regular SQRT CSLA architecture.

Modified 16-b Square-root Low Power Area Efficient Carry Select Adder

Due to acceptance of the portable system with fast growth of power density in the integrated circuits, the power dissipation and the performance is considered while the system is designed. The main goal of the VLSI design is to design the adders in more efficient way. By that way the Carry Select Adder (CSLA) is an adder designed, which computes n+1 bit sum of two n bit numbers. In this study Modified 16-b SQRT with Modified Area efficient CSLA is proposed. From the design of Modified Area Efficient CSLA it is experiential that there is an option of reducing the area more and consumes low power when compared with Regular CSLA. Modified Area Efficient CSLA (MA-CSLA) utilizes BEC which reduces the area more and the total gate count is also gets condensed. The proposed study makes use of a simple and well-organized gate-level alteration to considerably reduce the area and power of the CSLA. By the support of alteration 8-, 16-, 32- and 64-b, respectively Square-Root CSLA (SQRT CSLA) model have been evolved and evaluated with the regular SQRT CSLA model. This study estimates the performance of the proposed designs in terms of delay, area and power. The results analysis shows that the proposed Modified Area Efficient CSLA structure is better than the regular SQRT CSLA.

MINIATURE IMPROVED CARRY SELECT ADDER WITH ADVANCE FEATURES AND POWER REQUIREMENTS

In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Low Power 256-bit Modified Carry Select Adder

Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. When compared to earlier Ripple Carry Adder and Carry Look Ahead Adder, Regular CSLA (R-CSLA) is observed to provide optimized results in terms of area. This study proposes an efficient method which replaces the RCA using BEC. The modified CSLA architecture has been developed using gate-level modification to significantly reduce the delay and power of the CSLA. Based on this modification 8-, 16-, 32-, 64- and 128-bit Square-Root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design for 256-bit has reduced power and delay as compared with the regular SQRT CSLA. Designs were developed using structural Verilog module and synthesized using Xilinx ISE simulator and the implementation is done in cadence RTL compiler using 0.18 μm technology. For 256-bit addition in this study, it is proposed to simple gate level modification which significantly reduces the power by 19.4% when compared with R-CSLA. The result analysis shows that the proposed architecture achieves two folded advantages in terms of delay and power.

Implementation and Comparison of Vedic Multiplier using Area Efficient CSLA Architectures

In the design of Integrated circuits, area plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in many dataprocessing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 4 bit, 8 bit, 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root (SQRT) CSLA and Modified SQRT CSLA architectures have been developed and compared the area of these 4 types of CSLA and also applied these 4 bit, 8 bit, 16 bit, 32 bit, 64 bit and 128 bit CSLAs into 4X4 bit, 8X8 bit, 16X16 bit, 32X32 bit, 64X64 bit and 128X128 bit Vedic Multiplier (VM) respectively, then compared the area of Vedic Multiplier based on this adders. However, the Regular CSLA is still area consuming due to the dual Ripple Carry Adder (RCA) structure. For reducing the area of CSLA, it can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular CSLA with Modified CSLA, the Modified CSLA has less area. The results and analysis show that the Modified SQRT CSLA provides better outcomes like less area and also the Vedic Multiplier using Modified Linear CSLA provides less area. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLAs and VM using CSLAs and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex FPGA Kit.

Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Low Power High Speed SQRT Carry Select Adder

Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder among other. There is scope to reduce the power consumption in the regular CSLA. A simple gate level modification is required of the regular CSLA to reduce the power. This paper proposes modified 40-bit square-root CSLA (SQRT CSLA) architecture. Both the regular and modified 40-bit CSLA are designed with TSMC 0.13-µm CMOS process technology and results are compared with TSMC 0.18-µm CMOS process technology. The proposed design has reduced area and power as compared with the regular SQRT CSLA withy slight increase in the delay. The result analysis shows that proposed CSLA has better performance than conventional CSLA.