Spurious Level Research Articles

Particle spectroscopy of low-lying collective states in 100Ru

One neutron stripping and pick-up results obtained in São Paulo with good energy resolution show that levels interpreted in previous works as two-phonon and three-phonon states in 100Ru are excited with considerable intensity through predominantly direct one-step single neutron transfers. Furthermore, a comparative analysis of excitation energy values obtained in recent experiments, including the present results, with previous ones shows that there are at least 4 spurious levels in the adopted 100Ru level scheme below 2.5 MeV. Several levels seen in recent gamma work are here confirmed and three new ones indicated below 3.2 MeV of excitation energy.

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-/spl mu/m foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the /spl sim/43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is /spl sim/23 mW.

Scattering matrix approach to STW resonators.

The scattering matrix method was used for the analysis of surface transverse wave (STW) resonators on quartz. An expression for the transfer function of the resonators with different numbers of electrodes in the reflectors was derived. It was found that, for a proper ratio of these numbers, the spurious signal level below the resonance frequency can be lowered. The STW resonator for the frequency near 1090 MHz was designed, fabricated, and measured. By matching the measured and calculated transfer functions, the velocity, the electromechanical coupling coefficient, and the reflection coefficient of one aluminium strip of the STW on the 36 degrees Y-cut quartz were determined. The insertion loss about 7 dB, loaded quality coefficient near 4200, and the spurious signal level about 5 dB lower compared with the resonance one were obtained for the resonator.

A Voltage-Translinear Based CMOS Signal Component Separator Chip for Linear LINC Transmitters

The LINC transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. One crucial signal processing function of LINC is the signal component separator (SCS) which forms two constant-amplitude phase-modulated signals from the source signal. This paper presents an analog SCS chip implemented in a 0.35 μm CMOS process using a novel design based on the so-called voltage-translinear circuit principle. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that all output spurious levels some -55{\rm dBc} and -48 dBc could be obtained with a North American Digital Cellular (NADC) signal and an IS-95 signal, respectively. This implies a high degree of linearity.

A GMSK modulator using a /spl Delta//spl Sigma/ frequency discriminator-based synthesizer

This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of /spl Delta//spl Sigma/ frequency discriminator (/spl Delta//spl Sigma/FD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a /spl Delta//spl Sigma/FD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-/spl mu/m BiCMOS /spl Delta//spl Sigma/FD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz.

A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation

A mathematical approximation for the sine function is proposed which is so close to the sine function that it satisfies the accuracy requirements for sine computation in a typical sine-output direct digital frequency synthesizers (DDS). Then, it is shown that the proposed approximation is realizable by standard digital circuitry, so, a novel ROM-less architecture for sine-output DDS is developed, optimized, and implemented. Experimental results for the implemented ROM-less sine-output DDS are in complete agreement with simulation results in showing that the approximation error will cause harmonic levels below the spurious levels associated with the output quantization error. Another important advantage of the proposed architecture is that it dispenses with ROM, so it can be easily pipelined in order to be as fast as is required.

A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-/spl mu/m CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm/sup 2/ and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively.

Spurious signals in direct digital frequency synthesizers due to the phase truncation

Direct digital frequency synthesizers (DDS or DDFS) are widely used in modern communications and measurement devices. Their advantages are small size and power consumption together with excellent frequency stability, high frequency resolution, and short switching times. The difficulties are rather low output frequencies (500 MHz at the present state of the art) and a large set of the spurious signals very often above the -80 dB level. One source of spurious signals in DDS is the use of smaller number, W, of the most significant bits (MSB) applied for the output sine wave reconstruction from all R bits stored in the accumulator. The result is a phase modulation of the output signal. The problem was first solved in a rather complicated way with the result that the level of the largest spurious signal is about -6 W dB below the carrier with an increase of 3.9 dB in some instances. A simpler solution of the problem of spurious signal level due to the phase truncation in DDS was found earlier. However, no attention was paid to the validity of the corrections suggested. In this paper we will be concerned with this problem and investigate the validity and correctness of these generally cited results and provide a simple way for finding positions, levels, and numbers of these spurious signals generated by truncation to W bits of the phase information stored in the DDS accumulator memory of R bits (W<R).

A 200-MHz IF BiCMOS signal component separator for linear LINC transmitters

The linear amplification with nonlinear components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial signal processing function of LINC. It forms two constant-amplitude phase-modulated signal components from the input signal. Due to the nonlinear signal processing involved, digital signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 /spl mu/m BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a /spl pi//4-shifted DQPSK modulated North American Digital Cellular (NADC) signal. This implies a high degree of linearity in the implemented LINC transmitter.

A phase-interpolation direct digital synthesizer with an adaptive integrator

A phase-interpolation direct digital synthesizer (DDS) with an adaptive integrator is described in this paper. Unlike a conventional DDS, it does not use ROM or a D/A converter. Therefore, less power is dissipated and the maximum speed is increased. The delay time for phase interpolation is generated by the adaptive integrator, which is composed of a capacitance switch array and current switch array, and by a comparator with constant threshold voltage. The DDS was fabricated on 0.5-/spl mu/m CMOS process technology. The spurious level is lower than -50 dBc and the power dissipation is 60 mW at a clock frequency of 40 MHz and output frequency of about 19 MHz.

A Wide-Bandwidth-Output Direct Digital Synthesizer with Multiple Delay Generators

A new type of phase interpolation direct digital synthesizer (DDS) that can generate signals up to the clock frequency is proposed. The maximum output frequencies of conventional DDSs are limited to half the clock frequencies. To eliminate this frequency limit, we designed a new ROM-less DDS with multiple delay generators that are mutually triggered by a pulse distributor. Pulse distribution plays an important role in reducing the effective resetting time of the delay generators. We derived a theoretical expression which gives the maximum output frequency of the new DDS. According to the expression, the maximum output frequency can be determined by the number of delay generators and maximum leaking time. We also show that the new DDS can produce output signals up to the clock frequency with three or four delay generators. Experimental results confirm frequency synthesizer operation in which the spurious level is reduced by the delay generators. The results also confirm that the maximum output frequency is not limited to half the clock frequency when using two delay generators. This is consistent with the theoretical expression.

Evaluation of Accelerometer Mechanical Filters on Submerged Cylinders Near an Underwater Explosion

An accelerometer, mounted to a structure near an explosion to measure elasto-plastic deformation, can be excited at its resonant frequency by impulsive stresses transmitted within the structure. This results in spurious high peak acceleration levels that can be much higher than acceleration levels from the explosion itself. The spurious signals also have higher frequencies than the underlying signal from the explosion and can be removed by a low pass filter. This report assesses the performance of four accelerometer and filter assemblies. The assessment involves measurements of the response of a mild steel cylinder to an underwater explosion, in which each assembly is mounted onto the interior surface of the cylinder. Three assemblies utilise a piezoresistive accelerometer in which isolation is provided mechanically. In the fourth assembly, a piezoelectric accelerometer, with a built-in filter, incorporates both mechanical and electronic filtering. This assembly is found to be more suitable because of its secure mounting arrangement, ease of use, robustness and noise free results.

Low-power dividerless frequency synthesis using aperture phase detection

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLL's loop bandwidth is measured to he 6 MHz, with a reference spurious level of -47 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process and operates on a 2.5-V supply.

Digital frequency synthesizer/modulator for continuous-phase modulations with slow frequency hopping

This paper gives a description of a modulator for burst-by-burst carrier frequency hopping in time-division multiple-access (TDMA) systems. The architecture consists of a digital frequency synthesizer/modulator for continuous-phase modulations (CPMs) and a fast frequency settling RF synthesizer consisting of one phase-locked loop (PLL). The performance of the digital frequency synthesizer/CPM modulator has been analyzed theoretically and simulated by a computer program. The analyses show that the proposed digital frequency synthesizer/CPM modulator achieves 2.5-W lower power consumption and 18-dB lower spurious levels than the fast frequency hopping systems synthesizing digitally a full frequency band. In the computer simulations the effect of the digital frequency synthesizer/CPM modulator parameters on the power spectrum and the phase error is investigated.

Differential analysis of codaQusing similar microearthquakes in seismic gaps. Part 2: Application to seismograms recorded by the Parkfield High Resolution Seismic Network

AbstractNearly two-thirds of the microseismicity occurring at Parkfield, California, consists of repeating clusters of closely located events exhibiting waveform cross-correlation values exceeding 0.95. This observation, coupled with a high probability for an M ≈ 6 earthquake within the next decade (Working Group on California Earthquake Probabilities, 1988), make this segment of the San Andreas fault system a prime location to search for temporal variations in coda Q associated with crustal changes that may occur during the earthquake cycle. The coda comparison analysis method described in Part 1 of this study (Aster et al., 1996) is applied to data from four borehole stations of the Parkfield High Resolution Seismic Network (HRSN) for the period January 1987 through February 1994. We examine 21 of the nearly 300 repeating clusters observed to date. The restriction of the data set to only the most highly similar sources is observed to be critical; small differences in the source process, even for event pairs with centroid locations within approximately 20 m, significantly increase the spurious noise level in the parameter estimates. Absolute 68% confidence bound estimates obtained on the repeatability of coda Q for all microearthquake pairs are ±10% for frequencies below 20 Hz. Tighter constraints are obtainable by reconstructing the temporal history of coda Q from the first difference measurements between microearthquake pairs. These functional reconstructions show that the mean value of coda Q has not varied by more than approximately 5% from 3 to 30 Hz at the 1σ level during the study period. However, other observables, such as an increased level of microseismicity, suggest that a preparatory stage for the next Parkfield earthquake has begun, indicating that coda Q is so far showing no sign of sensitivity to preparatory processes at Parkfield.

The Fourier transform as a signature for chaos in nuclear energy levels

The Fourier transform of the autocorrelation function is an alternative test to characterize level statistics. For GOE statistics there is a suppression of the Fourier transform near the origin; this correlation hole is absent for Poisson statistics. Numerical modeling has been used to quantify the method and determine the dependence of the correlation-hole area on number, density, sampling interval, and fraction of missing or spurious levels. For large N the normalized correlation-hole area is a nearly universal constant and insensitive to missing and spurious levels. However, for the smaller sample sizes typical of nuclear data, application of the FT method yields ambiguous results.

Parity dependence of the nuclear level density at high excitation

Abstract The basic underlying assumption ϱ(l + 1, J) = ϱ(l, J) in the level density function π(U, J, π) has been checked on the basis of high quality data available on individual resonance parameters (E0, Γn, Jπ) for s- and p-wave neutrons in contrast to the earlier analysis where information about p-wave resonance parameters was meagre. The missing level estimator based on the partial integration over a Porter-Thomas distribution of neutron reduced widths and the Dyson-Mehta Δ3 statistic for the level spacing have been used to ascertain that the s- and p-wave resonance level spacings D(0) and D(1) are not in error because of spurious and missing levels. The present work does not validate the tacit assumption π(l + 1, J) = π(l, J) and confirms that the level density depends upon parity at high excitation. The possible implications of the parity dependence of the level density on the results of statistical model calculations of nuclear reaction cross sections as well as on pre-compound emission have been emphasized.

Wideband phase‐locked loop synthesizer using linear frequency variation direct digital synthesizer as reference oscillator

AbstractA wideband phase‐locked loop (PLL) synthesizer is proposed in which a linear frequency variation direct digital synthesizer (LFDDS) is used as a reference oscillator and a frequency variation band can be widened up to the full tunable range of voltage controlled oscillator (VCO) by frequency hopping within the lock‐in range of PLL. A. theoretical study is made and experimental results are explained. At first, assuming continuous frequency variation of LFDDS, transient behavior of frequency difference between two input signals of phase comparator of PLL is determined. Next, the condition for frequency variation speed of LFDDS is derived so that phase locking can be obtained using the maximum value of this frequency difference. Then the quantized frequency variation of LFDDS is assumed, transient behavior of the frequency difference is determined, and its difference from the continuous variation is clarified. A 6‐GHz band PLL synthesizer is fabricated, and the theory's validity is confirmed through experiments. Using LFDDS, a frequency setting time for a PLL synthesizer increases less than 10 percent for five times wider operation bandwidth. Performing experiments in 79 6‐GHz band. we obtained an operation bandwidth of 23 percent and so frequency hopping can be performed. Moreover, a frequency setting time of 50 μs and spurious level of ‐55 dBc were obtained.

An X-band acousto-optic variable delay line for radar target simulation

The design and characterization of a 54-/spl mu/s, continuously-variable, acousto-optic (AO) delay line developed for radar testing applications is presented. Design goals for the delay line include over 10 MHz of instantaneous bandwidth, 1.2 GHz of tunable bandwidth operating at X-band, 45 dB of dynamic range, and electronically-controllable delay selection to simulate dynamic radar targets with radial range rates up to 500 m/s. In addition, the device was designed to have phase noise and spurious signal levels compatible with high performance radars. To achieve these goals, a 33-MHz center frequency variable delay line was constructed and coherent frequency translation was used to provide operation at S-band. Operating principles for this new intermediate frequency (IF) delay line are presented, and key component issues are discussed. A computer design and analysis tool is described that predicts delay line performance. Experimental results are presented at both the IF and at X-band. >

High‐speed frequency‐switching synthesizer using fractional N phase‐locked loop

AbstractA fractional N phase‐locked loop frequency synthe sizer has been developed for small‐size and low‐power applications. It has fast frequency switching and low‐phase noise. the fractional N‐frequency synthesizer realizes fast switching by the high‐frequency reference signal and by widening the loop bandwidth. However, when the bandwidth was widened, deterioration of phase noise is observed. Then the loop bandwidth which is necessary for fast frequency switching and which gives low‐phase noise performance is determined.Based on these conditions, loop filter switching was studied which realized fast switching by widening the loop bandwidth and the low‐phase noise performance by making the loop bandwidth narrow after the frequency switching. In the conventional filter switching, VCO control voltage fluctuates at the time of switching and the frequency switching time becomes longer.A new method is proposed which gives small switching fluctuation and which can shorten the frequency switching time. Finally, the synthesizer circuit in the 900‐MHz band was fabricated and the lock‐up time of 1.3 ms, the phase noise of ‐120 dBc/Hz at 50 kHz offset from carrier and spurious level of ‐83 dBc were obtained.