Spin-on Glass Research Articles

Localized surface plasmon-enhanced nanorod micro-LEDs with Ag nanoparticles embedded in insulating and planarizing spin-on glass

To enhance the emission of GaN-based Micro-LEDs (μLEDs), we etched uniform nanorods (NRs) on the μLED surface and filled the nanorod gaps with spin-on glass (SOG) containing mixed Ag nanoparticles (NPs). The nanorod structure creates a conducive environment for close interaction between Ag NPs and quantum wells (QWs), facilitating the coupling of Ag NPs as localized surface plasmons (LSPs) with the QWs to enhance light emission. The SOG acts as an insulating layer between Ag NPs and NRs, preventing electron leakage, while also serving as a planarization material for the nanorod structure. This configuration allows for the fabrication of a planar Indium Tin Oxide layer without short-circuiting the nanorod structure. Compared to traditional planar Micro-LEDs, NR-μLEDs with SOG-encased Ag NPs exhibit a 50% increase in electroluminescence (EL) intensity and a 56% increase in photoluminescence (PL) intensity. This work paves the way for broader applications of LSP in μLEDs.

New Scheme of Microlens Fiber Array for High Coupling Efficiency in Si-Photonics Module

A new scheme of microlens 4-fiber array (M4FA) for high-coupling efficiency in Si-photonics module employing automatic packaging a silicon V-groove array and microlens fibers is demonstrated. The silicon V-groove array was fabricated by KOH wet etching. The microlens fibers were precisely controlled by automatic grinding and calibrated spin-on-glass (SOG) liquid electrostatic coating to achieve the required minor radius of curvature of 1.3- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> for achieving high coupling efficiency. In comparison with other microlens fabrication by mechanical grinding and multiple fusing techniques, the proposed M4FAs enable to adjust the fiber offset, radius of curvature, and alignment tolerance by SOG coating after fiber grinded, resulting in high-average coupling efficiency of 60% from Si-photonics module to M4FA. The newly developed M4FA by automatic grinding and calibrated SOG coating is beneficial for the applications of Si-photonics modules use in many low-cost and high-performance light-wave interconnections.

Pt and Pd Nanoparticle Crystallization in the Sol-Gel-Derived Thin SiO2 Films

The crystallization and distribution the features of Pt, Pd and Pt/Pd nanoparticles in spin-on glass SiO2 films were studied within a wide range of the dopant concentrations in silica sol (from 10 to 80 mol.% Pt, Pd or Pt/Pd per 100 mol.% Si). The grazing incidence X-ray diffraction (GIXRD) characterization revealed that the formation of 4–8 nm sized crystalline Pt, Pd and Pt/Pd nanoparticles in SiO2 films began at the dopant concentrations of at least 10 mol.% Pt and/or Pd per 100 mol.% Si. The nanoparticles obtained from sols with the lower Pt, Pd or Pt/Pd concentrations were characterized by an amorphous structure. The dopants distribution over the film thickness (~21–47 nm) was studied using X-ray reflectometry. The effect of the dopant concentration, spin-coating modes and heat treatment temperature on the film thickness was characterized. When only one of the dopants (Pt or Pd) was introduced into the silica sol, the resulting nanoparticles were preferentially localized close to the film surface. When dopants were used together, the Pt/Pd nanoparticles were distributed more evenly.

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

AbstractCarbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date.image

Ex-situ phosphorus-doped polycrystalline silicon passivating contacts for high-efficiency solar cells by physical vapour deposition

We present ex-situ phosphorus-doped polycrystalline silicon (poly-Si) passivating contacts fabricated by the physical vapour deposition method, specifically sputtering. This technique is currently of great interest to the photovoltaics (PV) community due to its low deposition temperature, small footprint, high throughput, and use of low-hazard, solid targets and gases. We optimise the performance of the passivating contacts by adjusting various parameters from the sputtering of amorphous Si films to the formation of the poly-Si layers by a high-temperature thermal diffusion (with phosphorus oxychloride – POCl3, or phosphorus spin-on glass as the dopant sources). For the case of POCl3 diffusion, a high iVoc of ∼720 mV together with a low J0 of 2.6 fA/cm2 after a hydrogenation treatment by atomic layer deposition (ALD) AlOx and forming gas annealing (FGA), and a low contact resistivity ρc of less than 10 mΩ cm2 were achieved. Meanwhile, with spin-on doping, a low average iVoc of ∼600 mV was observed. This variation in performance could be explained by the difference in the crystallinity and the diffusion mechanism of the sputtered Si films after different subsequent thermal diffusion processes. Quokka3 simulations show that cell efficiencies as high as 25% are possible using the optimised passivating contacts. The results demonstrate the potential of these PVD poly-Si films as a promising candidate for future industrial solar cells.

Evolution of lithography-to-etch bias in multi-patterning processes

Quantitatively accurate, physics-based, computational modeling of etching and lithography processes is essential for modern semiconductor manufacturing. This paper presents lithography and etch models for a trilayer process in a back end of the line manufacturing vehicle. These models are calibrated and verified against top-down scanning electron microscope (SEM) and cross-sectional SEM measurements. Calibration errors are within 2 nm, while the maximum verification error is less than 3 nm. A fluorocarbon plasma etch of the spin-on-glass (SOG) layer accounts for most of the etch bias present in the process. The tapered profile in the SOG etch step is generated due to the polymerization process by fluorocarbon radicals generated in the plasma. The model predicts a strong correlation between the etch bias in the SOG etch step and the neutral-to-ion flux ratio in the plasma. The second etch step of the flow, which etches the spin-on-carbon (SOC) layer using an H2/N2 plasma, results in a negative etch bias (increase in CDs) for all measured features. The ratio of hydrogen to nitrogen radical fluxes effectively controls the etch bias in this step, with the model predicting an increase in the etch bias from negative to positive values as the H-to-N ratio decreases. The model also indicates an aspect ratio dependent etch rate in the SOG and SOC etch steps, as seen in the etch front evolution in a three-dimensional test feature. The third and final step of the process, SiO2-etch, generates an insignificant etch bias in all the test structures. Finally, the accuracy of the etch simulations is shown to be dependent on the accuracy of the incoming photoresist shapes. Models that consider only the top-down SEM measurement as input and do not account for an accurate photoresist profile, suffered significant errors in the post-etch CD predictions.

Plasma-based area selective deposition for extreme ultraviolet resist defectivity reduction and process window improvement

Extreme ultraviolet (EUV) lithography has overcome significant challenges to become an essential enabler to the logic scaling roadmap. However, it remains limited by stochastically driven defects, such as line breaks and line bridges for aggressive pitches. This is especially relevant for the back end of line, which requires the most aggressive scaling. Stochastic defects reduce device yield and may push device manufacturers to move to EUV multipatterning beyond 36 nm pitch single exposure, which is a costly option. While the lithography and patterning stack can be optimized to provide the largest process window with the lowest number of defects, process margins decrease as smaller pitches are required. Currently, for some lithography stacks, especially spin-on glass based trilayer stacks, the defect-free process window beyond 36 nm pitch is limited by line collapse. Reduction in resist thickness may mitigate pattern collapse, but it may also increase the number of line breaks—trading one killer defect for another. In this paper, we expand on an area selective deposition (ASD) process in situ of an etch chamber to selectively deposit material on the EUV photoresist prior to transferring the pattern downstream. We demonstrate mitigation of resist line notching and breaks while maintaining deposition-free open areas and clear alignment marks. Due to the inherent chemical selectivity of the deposition process as opposed to a purely aspect ratio driven deposition process, thinner resists that, with a normal etch condition would result in line breaks, can now be considered. This drives down flopover defect issues seen with thicker EUV resists and enables several underlayer systems that could otherwise not be considered. Finally, we demonstrate that defectivity levels measured by e-beam inspection post lithography and post pattern transfer and yield are both improved at 30 nm pitch when this ASD process is used.

2.8 kV Avalanche in Vertical GaN PN Diode Utilizing Field Plate on Hydrogen Passivated P-Layer

A novel edge termination method resulting in an avalanche-capable 2.8 kV vertical gallium nitride (GaN) pn diode is reported. A low transition temperature spin-on-glass (SOG) based field plate (FP) was deposited on top of the hydrogen-plasma passivated p GaN layer to achieve better electric field management. The hydrogen plasma treatment along with the field plate offered an edge termination without mesa etch that was able to mitigate the peak electric fields in the diodes. Avalanche was confirmed by the positive temperature coefficient of the breakdown voltage. Without the field plate, the breakdown voltage was recorded between 1.3 to 2.1 kV, without an avalanche behavior. The fabricated diodes exhibited a good rectifying behavior with an on-off ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{9}}$ </tex-math></inline-formula> and a specific resistance of 1.65 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This work demonstrated the avalanche capability with the combination of FP and hydrogen-plasma based termination in GaN vertical pn diodes, showing a high figure-of-merit of 4.8 GW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Ultrasensitive and Broadband Optical Toroidal Modes in all‐Dielectric Nanostructures (Laser Photonics Rev. 16(3)/2022)

Toroidal Metamaterials In article number 2100404, Hui-Hsin Hsiao, and Ai-Yin Liu demonstrate optical toroidal dipole and anapole metamaterials through the designs of periodic amorphous silicon nano-pillars embedded in a spin-on glass layer. Upon normal incidence of plane wave, the transverse toroidal moment, stemming from a complete head-to-tail configuration of the magnetic dipole moments within each individual nanopillar, are excited in optical regime. The toroidal response can be enhanced and spectrally tuned by elongating cylindrical axis perpendicular to the light polarization and exhibit ultrahigh refractive index sensitivity compared to other multipoles.

Fabrication and Characterization of 2-Bit per Capacitor as Functional Structures for Physical Unclonable Function Circuits

Currently, security issues for semiconductor chips are counterfeiting and night shift problems. These factors might lead to insecure supply chains in the automotive industry. This can be avoided by using coating Physical Unclonable Functions (PUFs). The coating can be applied to every semiconductor chip in order to create a unique fingerprint. In this work, a 2-bit key per capacitor for Physical Unclonable Functions is presented for the first time. For this reason, 49 chips on a wafer with 195 metal oxide semiconductor (MOS) capacitors were fabricated. A large and random fluctuation of the capacitances was achieved by using a self-developed layer, which consisted of aluminum particles and spin-on glass. Due to the random variation in size and change in distribution of the particles, the fluctuation of capacitance varied from chip to chip and from wafer to wafer. The achieved large range in capacitance was used to create a 390-bit string out of 195 capacitors. Although the length of the bit string was doubled, the area of the structure remained constant. This led to a more secure PUF with a low error rate of 0.21% and an inter-chip Hamming distance (HD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inter</sub> ) of 49%.

Diffusion properties of n-type dopants diffused from spin on glass into Ge

Solid phase diffusion properties of three typical n-type dopants (P, As, and Sb) in Ge have been studied through experimental depth profiles of dopants diffused from spin on glass (SOG) films. Numerical calculations of dopant profiles in Ge are performed to extract the diffusion constant through comparison with the experimental profiles. It is pointed out that experimental results of diffusion at low temperature are important to correctly examine the influence of negative charge states of a vacancy on dopant diffusion. It is found that vacancies with the charge states of −2 mediate the diffusion of P and As without implantation-induced defects. The diffusion constants of P and As, obtained in this study, are larger than those for intrinsic diffusion, while that of Sb is almost the same as that for intrinsic diffusion. The present larger diffusion constants of P and As can be explained by the supply of vacancies from Ge surfaces via E-centers during diffusion from SOG.

Stability of zinc nitride thin-film transistors under positive and negative bias stress

In this work, the electrical stability of zinc nitride (Zn3N2) Thin-film Transistors (TFTs) under negative bias stress (NBS) and positive bias stress (PBS) is presented. The Zn3N2 TFTs were fabricated on plastic substrates. Spin-on glass was used as gate dielectric. The threshold voltage shift (ΔVT) and its recovery are analyzed during a long stress time and after a period of rest. The hysteresis of the transfer characteristics after the electrical stress is also analyzed. In order to explain the mechanism of instability in the Zn3N2 TFTs, MOS capacitors were fabricated and characterized under NBS and PBS. The behavior exhibited in MOS capacitors under NBS and PBS, is in agreement with the ΔVT exhibited in the Zn3N2 TFTs under NBS and PBS, respectively.

Fractals, morphogenesis and triply periodic minimal surfaces in sol–gel-derived thin films

The paper briefly reports on a contemporary view of the fractal structure of tetraethoxysilane (TEOS)- derived sol–gel synthesis products including in the presence of inorganic dopants and organic modifiers (H3PO4, polyionene, i.e., a high molecular weight quaternary ammonium compound, and epoxy resin), relying on the author’s and literature data. Morphological features of thin film surfaces and the effect of additives of inorganic salts and acids (Co(NO3)2, Al(NO3)3, H3BO3, HNO3, and HCl) thereon were analysed. The influence of spin-coating conditions (temperature and relative humidity) was also investigated, as exemplified by borosilicate “spin-on glass” films. The major components of film-forming TEOS-derived sols (TEOS and H3BO3, TEOS and epoxy-resin) were considered as morphogens. Moreover, their contribution to the formation of 2D and 3D stable spatial structures that were close to Turing patterns according to their configuration was assayed. An opportunity of formation of triply periodic minimal surfaces in thin-layer structures in the result of self-organization of viscous epoxy-siloxane sols has been discussed.

Review on modeling and application of chemical mechanical polishing

Abstract With the development of integrated circuit technology, especially after entering the sub-micron process, the reduction of critical dimensions and the realization of high-density devices, the flatness between integrated circuit material layers is becoming more and more critical. Because conventional mechanical polishing methods inevitably produce scratches of the same size as the device in metal or even dielectric layers, resulting in depth of field and focus problems in lithography. The first planarization technique to achieve application is spin on glass (SOG) technology. However, this technology will not only introduce new material layers, but will also fail to achieve the global flattening required by VLSI and ULSI technologies. Moreover, the process instability and uniformity during spin coating do not meet the high flatness requirements of the wafer surface. Also, while some techniques such as reverse etching and glass reflow can achieve submicron level regional planarization. After the critical dimension reaches 0.35 microns (sub-micron process), the above methods cannot meet the requirements of lithography and interconnect fabrication. In the 1980s, IBM first introduced the chemical mechanical polishing (CMP) technology used to manufacture precision optical instruments into its DRAM manufacturing [1]. With the development of technology nodes and critical dimensions, CMP technology has been widely used in the Front End Of Line (FEOL) and Back End Of Line (BEOL) processes [2]. Since the invention of chemical mechanical polishing, scientists have not stopped studying its internal mechanism. From the earliest Preston Formula (1927) to today’s wafer scale, chip scale, polishing pad contact, polishing pad - abrasive - wafer contact and material removal models, there are five different scale models from macro to the micro [3]. Many research methods, such as contact mechanics, multiphase flow kinetics, chemical reaction kinetics, molecular dynamics, etc., have been applied to explain the principles of chemical mechanical polishing to establish models. This paper mainly introduces and summarizes the different models of chemical mechanical polishing technology. The various application scenarios and advantages and dis-advantages of the model are discussed, and the development of modeling technology is introduced.

Effect of the spin-on-glass curing atmosphere on In–Ga–Zn–O thin-film transistors

A solution-based spin-on glass (SOG) was applied to the gate insulator of an oxide thin-film transistor (TFT). The curing atmosphere of the SOG was investigated to enhance the performance of the self-aligned top-gate In–Ga–Zn–O (IGZO) TFT. After the SOG layer was formed on an IGZO active layer, curing was performed under N2, air, and O2 atmospheres. The curing under an N2 atmosphere resulted in the best device characteristics for the IGZO TFT. After curing, the SOG films were investigated via atomic force microscopy, secondary ion mass spectroscopy, Fourier transform infrared spectroscopy, and capacitance measurement. The results showed that the N2 pile-up at the back surface of the SOG is the main reason for the enhanced performance of the TFT after curing under an N2 atmosphere.

Strain sensor with low thermal conductivity concealing resin for enhanced detection sensitivity and improved spatial resolution

An advanced thermoresistive strain sensor was proposed and realized with a concealing layer in this work, in which the heat transfer by conduction and convection for Joule heating-induced thermal energy were different from the existing sensor. Because the existing sensor was with a structure concealed by air and the proposed concealing layer in the advanced sensor was composed of polymeric materials, studies were made on the impacts generated by different concealing materials. Results indicated that conductions of heat transfer of solid spin-on glass and resin were that, although stronger than that of gaseous air, the heat transfer by convection in solid materials were negligible for enhanced performance. Results also indicated that the sensor with a solid concealing layer outperformed in detection sensitivity than the sensor without a concealing layer, and a low thermal conductivity solid concealing layer outperformed a high thermal conductivity solid concealing layer. On average, the detection sensitivity was enhanced by 46.32% and 58.57% for tension and compression in terms of background temperature-based gauge factor, respectively. Theoretical designs, numerical simulations, fabrications, analyses, and discussions were comprehensively provided in this work with additional case study on practical application of microscopic strain in a slightly deformed plastic substrate in a roll-to-roll manufacturing system as the proof-of-concept.

Vertical Ga2O3Schottky Barrier Diodes With Small-Angle Beveled Field Plates: A Baliga’s Figure-of-Merit of 0.6 GW/cm2

This letter demonstrates vertical Ga2O3 Schottky barrier diodes (SBDs) with a novel edge termination, the small-angle beveled field plate (SABFP), fabricated on thinned $\text{G}_{{2}}\text{O}_{{3}}$ substrates. Non-punch-though design is used for the drift region with a donor concentration of ${3}\sim {3.5} \times {10} ^{{16}}$ cm−3, rendering a device differential ON-resistance of $\sim 2~\text{m}\Omega ~\cdot $ cm2. A new wet-etch technique is developed by using a bi-layer mask, which consists of spin-on-glass (SOG) and plasma-enhanced chemical vapor deposited (PECVD) SiO2, to fabricate a very small bevel angle (∼ 1°) in the mesa and field plates. This SABFP structure facilitates the electric field spreading at device edges, rendering a breakdown voltage of 1100 V, a peak electric field of 3.5 MV/cm in Ga2O3 at the Schottky contact edge, and an averaged electric field over 3.4 MV/cm underneath the contact. Our device demonstrates a Baliga’s figure of merit of 0.6 GW/cm2, which is among the highest in all reported Ga2O3 power devices and comparable to the state-of-the-art GaN SBDs. These results show the great potential of Ga2O3 SBDs for future power applications.

Development of a Planarization Process for the Fabrication of Nanocrystalline Diamond Based Photonic Structures

A significant reduction of the intrinsic surface roughness of nanocrystalline diamond (NCD) layers (e.g., from 25–50 nm down to ≈ 2–6 nm) is accomplished together with an adjustment of the film thickness applying a two‐step planarization process. Therefore, a spin‐on‐glass (SOG), consisting of the inorganic polymer perhydropolysilazane, is spin‐coated on top of the NCD layer. After baking, a smooth silica‐like layer covered the diamond crystallites. This planar surface is transferred to the NCD surface by a dry etching step, yielding a similar etch selectivity for the diamond and the SOG layer (etching rates of SOG:NCD ≈ 1) applying a mixture of sulfur hexafluoride and oxygen. The planarized surface of the NCD layer led to an enhancement of the uniformity of structures defined by electron beam lithography (EBL), e.g., nanopillars with various diameters as well as two‐dimensional photonic crystal slabs.

Processes of film-formation and crystallization in catalytically active ‘spin-on glass’ silica films containing Pt and Pd nanoparticles

This research is devoted to the study of the composition and surface morphology of extremely thin ‘spin-on glass’ films (~20–50 nm) doped with Pt and Pd compounds in concentrations depending on the ratio of precursors in TEOS-derived sols, their aging time and heat treatment temperature.Such methods as spectrophotometry in visible and ultraviolet regions, atomic force and scanning microscopy, X-ray reflectometry, X-ray phase analysis and voltammetry were used to study processes of the formation of sols and films based on them.The authors of this study defined features of sol-gel processes based on acid hydrolysis of TEOS in presence of dopants (Pt and Pd compounds) taken separately and together. It was shown that the combination of two dopants (Pt and Pd compounds) taken in the mole ratio of 1:1 increases catalytic activity of the films towards hydrogen.

Scalable methods for ultra-smooth platinum in nanoscale devices

Ultra-smooth metal structures are increasingly important in nanoscale device applications, from photonics to molecular electronics and 2D material growth. We describe three methods for achieving ultra-smooth platinum: patterned template stripping, chemical mechanical polishing and giant grain growth. Specifically, we demonstrate 1) the first use of spin-on glass as an adhesive for the transfer of a patterned platinum film via template stripping, enabling the film to be exposed to harsher solvents and at higher temperatures; 2) an updated CMP process for platinum with slurry materials that are currently available; 3) a giant grain growth process on a 4″ quartz substrate that uses a thinner Pt film than previously reported. Overall, root mean squared film roughness was decreased from ~14 Å for as-deposited platinum to <4 Å, while improving on scalability and compatibility subsequent processing of pre-existing techniques.