Spin-on Carbon Research Articles

Controlled Anisotropic Wetting by Plasma Treatment for Directed Self-Assembly of High-χ Block Copolymers.

The directed self-assembly (DSA) of block copolymers (BCPs) is a promising next-generation lithography technique for high-resolution patterning. However, achieving lithographically applicable BCP organization such as out-of-plane lamellae requires proper tuning of interfacial energies between the BCP domains and the substrate, which remains difficult to address effectively and efficiently with high-χ BCPs. Here, we present the successful generation of anisotropic wetting by plasma treatment on patterned spin-on-carbon (SOC) substrates and its application to the DSA of a high-χ Si-containing material, poly(1,1-dimethylsilacyclobutane)-block-polystyrene (PDMSB-b-PS), with a 9 nm half pitch. Exposing the SOC substrate to different plasma chemistries promotes the vertical alignment of the PDMSB-b-PS lamellae within the trenches. In particular, a patterned substrate treated with HBr/O2 plasma gives both a neutral wetting at the bottom interface and a strong PS-affine wetting at the sidewalls of the SOC trenches to efficiently guide the vertical BCP lamellae. Furthermore, prolonged exposure to HBr/O2 plasma enables an adjustment of the trench width and an increased density of BCP lines on the substrate. Experimental observations are in agreement with a free energy configurational model developed to describe the system. These advances, which could be easily implemented in industry, could contribute to the wider adoption of self-assembly techniques in microelectronics, and beyond to applications such as metasurfaces, surface-enhanced Raman spectroscopy, and sensing technologies.

Dual layer chessboard metasurface sandwiched by a spin-on-carbon for spectral modulation.

Metasurfaces, composed by metals and dielectrics in periodical order with subwavelength pitches, are of great importance for their unique ability to abruptly manipulate optical fields. So far, all the reported metasurfaces are constructed by thermally deposited metals and dielectric films, based on semiconductor processes which are expensive and time-consuming. Inspired by the outstanding dry etch property of spin-on-carbon (SOC) as the interlayer material in CMOS technology, this paper proposes to utilize the SOC as the dielectric layer in a chessboard metasurface with dual layer of gold to form an array of local surface plasmonic resonators (localized surface plasmon resonance). Finite difference and time domain (FDTD) method is used to investigate the spectral characteristics in reflectance of the metasurface in both visible and short wavelengths of infrared light. Electron beam lithography is applied to generate the nanoscale chessboard pattern on ZEP520A, followed by a conventional oxygen-based plasma etch to form high aspect ratio nanopillar arrays in SOC with the feature width under 50 nm, and ended by a thermal deposition of gold to form self-aligned dual layer local surface plasmonic resonators (LSPRs). The measured reflectance spectra agree with the simulated. A wealth of optical properties, such as coupling induced modulations of spectra by LSPRs, are revealed and analyzed. These special modes result in tunable structural colors and wavelength-selective antireflection ability. To the best of our knowledge, this is the first time that SOC is applied in the construction of metasurfaces, which has great potential for next generation nanophotonic devices.

Nanoimprint with CO<sub>2</sub> Ambient

In Jet and Flash Imprint Lithography (JFIL), ambient gas is trapped between the resist, the substrate and the mold. The volume of the trapped ambient gas is estimated about 9.7 ~ 21.5% of the resist volume. It takes time for the bubbles to disappear in the closed space. By using carbon dioxide as the atmospheric gas and applying an organic layer such as Spin on Carbon (SOC) to the top surface layer of the substrate, it is proposed by theoretical calculation that the gas disappearance time is shortened and the throughput is improved. When the thickness of the SOC layer on the substrate was 5 nm or more, it was indicated that the gas disappearance time was shorter in carbon dioxide ambient than in helium ambient.

Evolution of lithography-to-etch bias in multi-patterning processes

Quantitatively accurate, physics-based, computational modeling of etching and lithography processes is essential for modern semiconductor manufacturing. This paper presents lithography and etch models for a trilayer process in a back end of the line manufacturing vehicle. These models are calibrated and verified against top-down scanning electron microscope (SEM) and cross-sectional SEM measurements. Calibration errors are within 2 nm, while the maximum verification error is less than 3 nm. A fluorocarbon plasma etch of the spin-on-glass (SOG) layer accounts for most of the etch bias present in the process. The tapered profile in the SOG etch step is generated due to the polymerization process by fluorocarbon radicals generated in the plasma. The model predicts a strong correlation between the etch bias in the SOG etch step and the neutral-to-ion flux ratio in the plasma. The second etch step of the flow, which etches the spin-on-carbon (SOC) layer using an H2/N2 plasma, results in a negative etch bias (increase in CDs) for all measured features. The ratio of hydrogen to nitrogen radical fluxes effectively controls the etch bias in this step, with the model predicting an increase in the etch bias from negative to positive values as the H-to-N ratio decreases. The model also indicates an aspect ratio dependent etch rate in the SOG and SOC etch steps, as seen in the etch front evolution in a three-dimensional test feature. The third and final step of the process, SiO2-etch, generates an insignificant etch bias in all the test structures. Finally, the accuracy of the etch simulations is shown to be dependent on the accuracy of the incoming photoresist shapes. Models that consider only the top-down SEM measurement as input and do not account for an accurate photoresist profile, suffered significant errors in the post-etch CD predictions.

Surface Transformation of Spin-on-Carbon Film via Forming Carbon Iron Complex for Remarkably Enhanced Polishing Rate.

To scale down semiconductor devices to a size less than the design rule of 10 nm, lithography using a carbon polymer hard-mask was applied, e.g., spin-on-carbon (SOC) film. Spin coating of the SOC film produces a high surface topography induced by pattern density, requiring chemical–mechanical planarization (CMP) for removing such high surface topography. To achieve a relatively high polishing rate of the SOC film surface, the CMP principally requires a carbon–carbon (C-C) bond breakage on the SOC film surface. A new design of CMP slurry evidently accomplished C-C bond breakage via transformation from a hard surface with strong C-C covalent bonds into a soft surface with a metal carbon complex (i.e., C=Fe=C bonds) during CMP, resulting in a remarkable increase in the rate of the SOC film surface transformation with an increase in ferric catalyst concentration. However, this surface transformation on the SOC film surface resulted in a noticeable increase in the absorption degree (i.e., hydrophilicity) of the SOC film CMP slurry on the polished SOC film surface during CMP. The polishing rate of the SOC film surface decreased notably with increasing ferric catalyst concentration. Therefore, the maximum polishing rate of the SOC film surface (i.e., 272.3 nm/min) could be achieved with a specific ferric catalyst concentration (0.05 wt%), which was around seven times higher than the me-chanical-only CMP.

High-efficiency diffraction gratings for EUV and soft x-rays using spin-on-carbon underlayers

We report on the fabrication and characterization of high-resolution gratings with high efficiency in the extreme ultraviolet (EUV) and soft x-ray ranges using spin-on-carbon (SOC) underlayers. We demonstrate the fabrication of diffraction gratings down to 20 nm half-pitch (HP) on Si3N4 membranes with a bilayer of hydrogen silsesquioxane (HSQ) and spin-on-carbon and show their performance as a grating mask for extreme ultraviolet interference lithography (EUV-IL). High-resolution patterning of HSQ is possible only for thin films due to pattern collapse. The combination of this high-resolution resist with SOC circumvents this problem and enables the fabrication of high aspect ratio nanostructures. Rigorous coupled-wave analysis shows that the bilayer gratings exhibit higher diffraction efficiency than what is feasible with a grating made of HSQ. We also demonstrate a simple and accurate method to experimentally measure the diffraction efficiency of high-resolution gratings by measuring the relative ratio of the dose-to-clear curves of the photoresist. The measured diffraction efficiencies are in good agreement with the theoretically predicted values. Furthermore, we verify our calculations and measurements by printing line/space patterns in chemically amplified resists down to 10 nm HP with both HSQ and bilayer grating masks using EUV-IL. The improved diffraction efficiency of the bilayers is expected to have applications not only in gratings for interference lithography, but also in Fresnel zone plates and gratings for spectroscopy in the EUV and soft x-ray ranges.

Line edge roughness reduction for EUV self-aligned double patterning by surface modification on spin-on-carbon and tone inversion technique

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER). In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects, which can lead to device degradation by defect formation and edge placement error (EPE). LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our study, we examine a technique to reduce LER on the EUV SADP line pattern. This technique involves the surface modification on the spin-on carbon (SOC) layer in the patterning stack and tone inversion process. We had found a trend between surface hydrophobicity of the SOC and the EUV SADP LER performance. The condition that increased the hydrophobicity of the SOC resulted in a lower LER performance after tone inversion. The tested conditions include direct current superposition (DCS) function with H2 plasma, fluorocarbon plasma, and the combination of DCS with H2 plasma and trimethylsilane dimethylamine deposition. On 20-nm pitch EUV SADP, this technique shows 26% of LER improvement from lithography to SADP formation. PSD analysis recorded about 6% and 30% of the LER improvement at the correlation length of >200 nm and 200 to 30 nm, respectively. A demonstration of this technique for a further scaling to 15-nm pitch also shows an LER reduction of 30% from lithography to SADP formation.

Removal of SOC Hard Mask for Patterning of Work Function Metal by Thermally Activated Ozone Gas

Thermally activated ozone gas (TAO) was demonstrated as an alternative technology to conventional spin-on carbon (SOC) stripping. The SOC stripping rate with ozone gas was found to be a function of substrate temperature and actual ozone amount calculated from the ozone flow rate and concentration. Furthermore, work function metal (WFM) stripping rate showed a high selectivity to SOC films, and the amount of oxidation TiN, which is a WFM metal, was also equivalent to conventional technology of SOC stripping. This TAO gas process can be used in clean tools, making it a promising integrated solution for SOC stripping followed by post clean.

Sub-20 nm Si fins with high aspect ratio via pattern transfer using fullerene-based spin-on-carbon hard masks

We report on a novel and simple pattern transfer process into Si via fullerene-based spin-on-carbon (SOC) hard masks in this work. Electron beam lithography and extreme ultraviolet interference lithography techniques are used to pattern high-resolution and dense lines on a resist/SOC bilayer. The patterns are subsequently transferred by a low-pressure O2 plasma etching (SOC) and reactive ion etching process with a gas mixture of SF6 and C4F8 (Si). Si sidewall trimming can be controlled by modifying the Si etching rate, achieving Si fins with dimension down to 15 nm half-pitch with aspect ratio as high as of 7:1.

The Improvement of the Pattern Wiggling Profile by Photo Resist Treatment

For advanced node such as 14nm technology and beyond, Patterning is one of the key challenges in the semiconductor industry. Advanced pattern transfer techniques such as negative tone development (NTD) technology are under investigation to enable the aggressive pitch requirements demanded. Even though, just as traditional positive tone development (PTD) technique, a pattern wiggling issue has arisen with the reduction of pattern dimension during dry etch process, which prevents the successful pattern transfer [1]. Two kinds of wiggling solutions have been proposed. One is the lithographic resolution such as changing the physical properties of the under-layer materials [2-4]. The other is the gases treatment in the tri-layer process such as H2plasma for spin-on carbon (SOC) hard-mask [5] and HBr and Ar plasma treatment for photoresist [6]. However, with the decrease of device size, a single method hardly eliminates wiggling and meets the pattern target. Besides, the requirements for Line Edge Roughness (LER)/Line Width Roughness (LWR); critical dimension uniformity (CDU); through pitch are extremely aggressive in advanced technology. Therefore, the characteristics of the dry etching process play an increasingly import role in defining the outcome of the pattern process. In this paper, we will demonstrate the method of PR treatment (both PTD and NTD techniques) that improves LER/LWR for trench pattern in dry etch ICP etcher. Meanwhile, the difference of PR treatment methods between PTD and NTD is illuminated. What’s more, in PR treatment methods, other pattern behavers such as CD, CD uniformity, through pitch are concerned during improving LER/LWR process, and aim to get a good result of all aspects. At last, the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR are studied. Acknowledgement REFERENCES [1] Goji Wakamatsu, Kentaro Goto, Yoshi Hishiro, Taiichi Furukawa al., Advances in Resist Materials and Processing Technology XXIX, Proc. of SPIE Vol. 8325 83250T-1,(2012) [2] Makoto, M., Mitsuaki, I., Takashi, K., Hisashi, H, and Seiji, F., Proc. SPIE7972,797226 (2011). [3] Tadokoro M., Yonekura K., Yoshikawa K., Ono Y., Ishibashi T., Hanawa T., Fukiwara N., Matsunobe T., MatsudaK., J. Vac. Sci.Technol. B,26, 67-71 (2008). [4] Someya, Y., Shinjo, T., Hashimoto, K., Nishimaki, H., Karasawa, R., Sakamoto, R., Matsumoto,T., Proceedings of the SPIE, vol.8325, 83250U (2012). [5] M. Tadokoro, K. Yonekura, K. Yoshikawa, Y. Ono, T. Ishibashi,T. Hanawa, and N. Fujiwara, J. Vac. Sci. Technol. B 26 (1) Jan/Feb( 2008) [6] E. Pargon, K. Menguelti, M. Martin, A. Bazin, O. Chaix-Pluchery, C. Sourd, S. Derrough, T. Lill, and O. Joubert, Journal of Applied Physics 105, 094902 (2009)

Progress and process improvements for multiple electron-beam direct write

Massively parallel electron beam direct write (MP-EBDW) lithography is a cost-effective patterning solution, complementary to optical lithography, for a variety of applications ranging from 200 to 14 nm. This paper will present last process/integration results to achieve targets for both 28 and 45 nm nodes. For 28 nm node, we mainly focus on line-width roughness (LWR) mitigation by playing with stack, new resist platform and bias design strategy. The lines roughness was reduced by using thicker spin-on-carbon (SOC) hardmask (−14%) or non-chemically amplified (non-CAR) resist with bias writing strategy implementation (−20%). Etch transfer into trilayer has been demonstrated by preserving pattern fidelity and profiles for both CAR and non-CAR resists. For 45 nm node, we demonstrate the electron-beam process integration within optical CMOS flows. Resists based on KrF platform show a full compatibility with multiple stacks to fit with conventional optical flow used for critical layers. Electron-beam resist performances have been optimized to fit the specifications in terms of resolution, energy latitude, LWR and stack compatibility. The patterning process overview showing the latest achievements is mature enough to enable starting the multi-beam technology pre-production mode.

Novel Spin on Planarization Technology by Photo Curing SOC (P-SOC)

In advanced lithography technology, high planarity SOC (Spin-on-Carbon) materials which can planarize topography substrates are required in order to obtain enough process margin. We developed photo curing SOC (P-SOC) materials which can be cross-link by short wavelength UV light, but not thermal process. The P-SOC can achieve high planarization and good via filling because they have high reflow performance without viscosity increasing by baking process and almost no film shrinkage during the baking and photo curing process. The novel P-SOC materials are suitable for very fine pattern manufacturing process as N5 generation which is needed planarization technology.

A novel simple sub-15 nm line-and-space patterning process flow using directed self-assembly technology

In order to evaluate process performances of directed self-assembly (DSA) lithography for semiconductor device manufacturing, we developed a novel simple sub-15nm line-and-space (L/S) patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP). The new process with grapho- and chemo-hybrid coordinated line epitaxy, using trimming resist and shallow etching spin-on-glass (SOG) as pinning guide, requires neither special pinning guide materials to control surface free energy on guideline patterns nor any resist strip process after guideline pattern fabrication. In this process, insolubility and thermal resistance of pinning guide are provided by shallow SOG etching deposition residue consisting of SOG-occurring Si and CF4 gas-occurring CF compound. By optimization of guide resist critical dimension (CD) and resist film thickness, the half-pitch (HP) 15nm L/S patterns after dry development were fabricated with the maximum dose margin of approximately 15%. The HP 15nm L/S DSA patterning after SOG full etching was demonstrated on 300mm wafer with 85 chips. The presence of characteristic 3-dimensional (3D) BCP internal defects related to PS short defects was suggested by observation at SOG half-depth etching condition, and defects could be minimized by optimization of neutral layer (NL) material and sufficient phase-separation annealing. The 15nm PS line patterns were transferred to SOG and spin-on-carbon (SOC) stacked substrate.

Pulsed transfer etching of PS-PDMS block copolymers self-assembled in 193 nm lithography stacks.

This work presents the graphoepitaxy of high-χ block copolymers (BCP) in standard industry-like lithography stacks and their transfer into the silicon substrate The process includes conventional 193 nm photolithography, directed self-assembly of polystyrene-block-polydimethylsiloxane (PS-b-PDMS) and pulsed plasma etching to transfer the obtained features into the substrate. PS-b-PDMS has a high Flory-Huggins interaction parameter (high-χ) and is capable of achieving sub-10 nm feature sizes. The photolithography stack is fabricated on 300 mm diameter silicon wafers and is composed of three layers: spin-on-carbon (SoC), silicon-containing anti-reflective coating (SiARC) and 193 nm photolithography resist. Sixty-nanometer-deep trenches are first patterned by plasma etching in the SiARC/SoC stack using the resist mask. The PS-b-PDMS is then spread on the substrate surface. Directed self-assembly (DSA) of the BCP is induced by a solvent vapor annealing process and PDMS cylinders parallel to the substrate surface are obtained. The surface chemistry based on SoC permits an efficient etching process into the underlying silicon substrate. The etching process is performed under dedicated pulsed plasma etching conditions. Fifteen nanometer half-pitch dense line/space features are obtained with a height up to 90 nm.

Spin-on carbon based on fullerene derivatives as hardmask materials for high-aspect-ratio etching

The advance of lithographic resolution has made it necessary to adopt extremely thin photoresist films for the fabrication of “2× nm” structures in order to mitigate problems such as resist collapse during development but limiting achievable etch depths at the same time. By using multilayer hardmask stacks, a considerable increase in achievable aspect ratio is possible. We have previously presented a fullerene-based spin-on carbon hardmask material capable of high-aspect-ratio etching. We report our latest findings in material characterization of an original and a modified formulation. By using a higher adduct derivative fullerene, the solubility in industry-friendly solvents and thermal stability could be improved. The etching performance and materials characteristics of the new higher-adduct fullerene hardmask were found to be comparable to those of the original hardmask.

Sub-30nm via interconnects fabricated using directed self-assembly

In this study, sub-30nm via interconnects were fabricated and fully integrated on a 300mm wafer using directed self-assembly lithography (DSAL). They were tested electrically and initial test results are reported. DSAL was applied on the via layer, which is connecting between the lower metal layer and the upper metal layer. A trilayer resist process was utilized for preparing a guiding pattern of graphoepitaxy. Exposure dose of 193nm immersion lithography was centered so that via size in spin-on-carbon (SOC) was just 70nm in diameter. Poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) solution was applied on the SOC pre-pattern, and then annealed in N2 atmosphere to induce micro-phase separation. PMMA domain was finally transferred into a dTEOS oxide film as a via hole. Via interconnects were fabricated using tungsten deposition followed by CMP. Intra-wafer variation of via resistance was measured and the correlation between the via resistance and the via dimension was discussed.

Development of Spin-on High Carbon Hard Masks for High Resolution Photolithography

Silicon and carbon rich hard masks such as SiON and amorphous carbon (ACL) are widely used for high resolution pattern generation in integrated circuit (IC) chip fabrications. Those hard masks are conventionally prepared through chemical vapor deposition (CVD) processes. CVD processes require extra capital investments and have low manufacturing throughput. Spin-on hard masks are prepared using coatable organic polymer-based formulations on regular wafer processing tracks. The process is less complex and has lower manufacturing cost. There are many challenges facing the development of formulations for spin-on carbon (SOC) hard masks for advanced IC applications. In this publication, chemical and physical properties and the lithographic performances of several SOC formulations will be reported.

Step and Flash Imprint of Fluorinated Silicon-Containing Resist Materials for Three-Dimensional Nanofabrication

Advanced fabrication of multiple-level three-dimensional nanostructures by step and flash nanoimprint lithography was studied. This study has been shown to be applicable to future nanofabrication endeavors in the industrial production of electronic devices and optical materials. Step and flash nanoimprint technologies using the newly fluorinated silicon-containing resist materials to prevent resist pattern collapse, contamination problem of the quartz template, and defect problems were demonstrated. High-quality nanoimprint patterning of 65 nm dense lines and other multiple-level three-dimensional nanostructures was achieved using the proposed material design and under ultraviolet nanoimprint conditions. The developed fluorinated silicon-containing resist material as a hard mask layer with a nonsilicon spin-on carbon material was found to be useful in producing high-aspect-ratio patterned structures by step and flash nanoimprint lithography.

Double patterning down to <inline-formula><math display="inline" overflow="scroll"><mrow><msub><mi mathvariant="normal">k</mi><mn>1</mn></msub><mo>=</mo><mn>0.15</mn></mrow></math></inline-formula> with litho trim

A practical approach, adopting a clever litho trim, to spacer double patterning is investigated in detail. In order to produce quarter-pitch small lines of dense arrays (with pitch fragmentation techniques), state-of-the-art ArF photoresists can be used with a subsequent trim etch, to get the tiny line widths on desired target. Critical dimension (CD) control during the trim etch process plays a crucial role. Therefore, we investigated the application of a litho trim in order to reduce the trim etch close to zero bias. This approach has the further advantage to allow the printing of small spaces together with small lines, which reduces the k1 and, therefore, the theoretical resolution. Applying CD trim by litho “overexposure,” thin ArF bilayer system (silicon containing resist on spin-on carbon underlayer) showed basic suitability at k1=0.146 at half pitch of 3xnm with a sufficient process window and a good CD uniformity after litho and after etch. ArF single-layer resists suffer from pattern collapse and resist thickness loss at defocus. For spacer deposition directly on resist, the control of profiles and film thicknesses is shown to be difficult using single-layer resists and more likely to be achieved with bilayer resists. It is also shown that spacer-based double patterning can generate good CD uniformity by use of bilayer resist and litho trim, both with an a-Si carrier and bilayer resist carrier (underlayer).

Improvement of the wiggling profile of spin-on carbon hard mask by H[sub 2] plasma treatment

The H2 plasma treatment for spin-on carbon (SOC) hard mask in the trilayer resist process is expected to serve as a reliable alternative to single layer resist process for 45nm nodes and beyond. The authors have investigated this treatment with a view to suppress the deformation of SOC by oxide etching. The wiggling profile of SOC drastically improves due to the formation of a thicker diamondlike amorphous carbon structure by the H2 plasma treatment with higher-energy hydrogen ions.