Spike Annealing Research Articles

Mineral Interface Doping: Hydroxyapatite Deposited on Silicon to Trigger the Electronic Properties

AbstractDoping silicon wafers without using highly toxic or corrosive chemical substances has become a critical issue for semiconductor device manufacturing. In this work, ultra‐thin films of hydroxyapatite (Ca5(PO4)3OH) are prepared by tethering by aggregation and growth (T‐BAG), and further processed by spike annealing. Via in situ infrared (IR), the decomposition of hydroxyapatite and intermixing with the native silicon oxide is observed already at temperatures as low as 200 °C. Phosphate transport through the native silicon oxide is driven by a phase transformation into a more stable thermal oxide. At 700 °C, diffusion of phosphorus into the sub‐surface region of oxide‐free silicon is observed. In situ IR combined with electrical impedance spectroscopy (EIS), time‐of‐flight secondary ion mass spectrometry (ToF‐SIMS), and X‐ray photoelectron spectroscopy (XPS) measurements allows to conclude that the phosphorus is: i) transported through the silicon oxide barrier, ii)) diffused inside the oxide‐free silicon, and iii) finally modified the electrical activity of the silicon wafer. To further explain the experimental findings, density‐functional theory (DFT) is used to demonstrate the extent of the effect of phosphorus doping on the electronic nature of silicon surfaces, showing that even small amounts of doping can have a measurable effect on the electrical performance of semiconductor wafers.

FEOL Monolithic Co-Integration of FeFET and CMOS on 8-Inch Wafer Using Laser Spike Annealing With Implementation of an FeFET Inverter

FEOL Monolithic Co-Integration of FeFET and CMOS on 8-Inch Wafer Using Laser Spike Annealing With Implementation of an FeFET Inverter

Thermal budget reduction for spike anneals in conventional RTP

Thermal budget reduction for spike anneals in conventional RTP

In-situ observation of Kr2+ irradiation induced amorphization on Ca10-xLax(PO4)6-x(SiO4)xF2 (x=1, 2 and 6)

Fluorapatite, with a formula of A10(XO4)6F2, is a potential immobilization waste form of high-level waste due to its variable composition and stable structure. In this study, Ca10-xLax(PO4)6-x(SiO4)xF2 (x=1, 2 and 6) compounds with different doping amounts were synthesized. Samples were in-situ irradiated by 800 keV Kr2+ ions in the temperature range of 293 K to 673 K, with a flux of ∼1.72 × 1012 Kr2+/(cm2·s). Each specimen was continuously irradiated until the Selected Area Electron Diffraction (SAED) pattern indicated that it was fully amorphous. The corresponding critical amorphous temperatures Tc for these apatites were 514 K, 612 K and 737 K, respectively. The incorporation of lanthanum and silicon significantly reduced the radiation tolerance of fluorapatites. In terms of structure, SiO44− with larger size is more difficult to migrate than PO43− during thermal spike annealing. Besides, the occupancy of La3+ was also analyzed using the Rietveld refinement method. It is found that the preference of La3+ for Ca2 sites reduces the stability of the apatite structure. The ionic and covalent properties of the samples are also discussed as an essential factor affecting radiation resistance. The covalent SiO44− is considered to have a greater impact on the irradiation performance than La3+, and this effect is enhanced with the increase of the doping amount. This study investigated the radiation-induced amorphization of lanthanum-silicon-doped fluorapatite, which is of great significance for the study of high-level waste immobilization materials with different loadings.

Dopant Activation Depth Profiling for Highly Doped Si:P By Scanning Spreading Resistance Microscopy (SSRM) and Differential Hall Effect Metrology (DHEM)

Heavily n-doped epitaxially grown Si layers are of great importance for source/drain (S/D) application in advanced node nMOS devices. For contact resistivity reduction, the dopant activation level is very important. Various techniques are being used to evaluate dopant activation in Si:P layers. Among these two methods are Scanning Spreading Resistance Microscopy (SSRM) and Differential Hall Effect Metrology (DHEM). SSRM uses an atomic force microscope equipped with a hard conductive probe that is scanned in contact mode on the cross-sectioned sample’s surface and measures spreading resistance. Measured resistance values as a function of depth are converted into resistivity and carrier concentration depth profiles using calibration measurements and conversion relationships. DHEM provides depth profiles of mobility, resistivity and carrier concentration through a semiconductor layer by making successive sheet resistance (Rs) and Hall voltage measurements using Hall effect/Van der Pauw techniques, as the electrically active thickness of the layer is reduced through successive oxidation steps. Controlled oxidation is achieved by electrochemical anodization. Data collected can then be processed to yield the depth profiles. In this contribution we have carried out SSRM and DHEM measurements on Si:P epi layers subjected to different processing conditions including annealing and ohmic contact fabrication. Secondary Ion Mass Spectrometry (SIMS) was used to measure the total (active + inactive) dopant profiles through the films. Effects of these processes on dopant diffusion and activation were studied and the results from DHEM and SSRM were compared.In-situ phosphorus (P) doped Si epi-layers were grown over 300mm diameter boron doped monitor wafers. While one set was kept as the reference, a second set was treated by a spike-annealing process at 1000 °C. In a third set a Ti/TiN contact fabrication process was carried out and the contact was removed before analysis. In the fourth set contact process was applied to the spike annealed wafer before removal of the Ti/TiN layers. Bulk sheet resistance measurements were made using 4-point probe (4PP) for all the samples. SSRM measurements were carried out at IMEC. Cross-shaped Van der Pauw test-patterns were formed on 8mmx8mm areas on the samples and DHEM measurements were performed at ALP. Figure below shows the dopant depth profiles obtained by SIMS and the carrier concentration profiles from DHEM and SSRM techniques for samples D02 (as deposited Si:P) and D03 (spike annealed). One can make some general observations from the data in this figure. The total dopant concentration as measured by SIMS is ~ 1.4E21/cm3. There is only a small difference in the total dopant distribution profiles (SIMS) between the as deposited sample and the spike annealed sample. However, the spike annealed sample shows much higher dopant activation as measured by DHEM. Carrier concentration is ~2.5x higher in sample D03 (~5E20/cm3) compared to sample D02 (~2E20/cm3). Activation levels measured by SSRM, however, are lower for both samples, and the peak carrier concentration value increases only slightly upon spike annealing, going from ~2E20/cm3 in sample D02 to ~2.2E20/cm3 in sample D03. DHEM clearly indicates the sharp interface between the p-type substrate and the n-type epi-layer and its depth calibration agrees well with the expected thicknesses of the epi layers. The tail of the SSRM data is much more graded. Data from other samples will be presented and discussed in the final manuscript. Figure 1

Atomistic Observation of the Local Phase Transition in MoTe2 for Application in Homojunction Photodetectors.

Direct atomic-scale observation of the local phase transition in transition metal dichalcogenides (TMDCs) is critically required to carry out in-depth studies of their atomic structures and electronic features. However, the structural aspects including crystal symmetries tend to be unclear and unintuitive in real-time monitoring of the phase transition process. Herein, by using in situ transmission electron microscopy, information about the phase transition mechanism of MoTe2 from hexagonal structure (2H phase) to monoclinic structure (1T' phase) driven by sublimation of Te atoms after a spike annealing is obtained directly. Furthermore, with the control of Te atom sublimation by modulating the hexagonal boron nitride (h-BN) coverage in the desired area, the lateral 1T'-enriched MoTe2 /2H MoTe2 homojunction can be one-step constructed via an annealing treatment. Owing to the gradient bandgap provided by 1T'-enriched MoTe2 and 2H MoTe2 , the photodetector composed of the 1T'-enriched MoTe2 /2H MoTe2 homojunction shows fast photoresponse and ten times larger photocurrents than that consisting of a pure 2H MoTe2 channel. The study reveals a route to improve the performance of optoelectronic and electronic devices based on TMDCs with both semiconducting and semimetallic phases.

Low-Frequency Noise Analysis of the Optimized Post High-k Deposition Annealing in FinFET Technology

The optimized postdeposition annealing (PDA) of the high- ${k}$ metal gate is investigated for 1/ ${f}$ noise performance improvement in FinFET technology by using spike annealing (SPA) and SPA-combined millisecond flash annealing (MFLA) treatment. It demonstrates that the additional MFLA can significantly reduce the 1/ ${f}$ noise without device performance degradation. Based on the low-frequency noise analysis, the reduced 1/ ${f}$ noise arises from the decrease in the density of interface traps ( ${D}_{\textit {it}}$ ) between Si-fin and interfacial layer (IL) that is prepared with $\text{O}_{{3}}$ -oxidation. Furthermore, the gate leakage is suppressed without equivalent oxide thickness (EOT) penalty, which is considered as the high- ${k}$ (HfO $_{{2}}{)}$ quality improvement from reducing oxygen vacancies and passivating the dangling bonds by forming a stronger Hf–N from additional MFLA.

Optical Identification of Materials Transformations in Oxide Thin Films.

Recent advances in high-throughput experimentation for combinatorial studies have accelerated the discovery and analysis of materials across a wide range of compositions and synthesis conditions. However, many of the more powerful characterization methods are limited by speed, cost, availability, and/or resolution. To make efficient use of these methods, there is value in developing approaches for identifying critical compositions and conditions to be used as a priori knowledge for follow-up characterization with high-precision techniques, such as micrometer-scale synchrotron-based X-ray diffraction (XRD). Here, we demonstrate the use of optical microscopy and reflectance spectroscopy to identify likely phase-change boundaries in thin film libraries. These methods are used to delineate possible metastable phase boundaries following lateral-gradient laser spike annealing (lg-LSA) of oxide materials. The set of boundaries are then compared with definitive determinations of structural transformations obtained using high-resolution XRD. We demonstrate that the optical methods detect more than 95% of the structural transformations in a composition-gradient La-Mn-O library and a Ga2O3 sample, both subject to an extensive set of lg-LSA anneals. Our results provide quantitative support for the value of optically detected transformations as a priori data to guide subsequent structural characterization, ultimately accelerating and enhancing the efficient implementation of micrometer-resolution XRD experiments.

Fabrication technique of the Si0.5Ge0.5 Fin for the high mobility channel FinFET device

In this paper, a fabrication technique of Si0.5Ge0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si0.5Ge0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si0.5Ge0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si0.5Ge0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si0.5Ge0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si0.5Ge0.5 Fin is already oxidized and SiGeOx has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si0.5Ge0.5 Fin loss with sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.

Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40 μA/μm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressed at the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decade was obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device

In this work, SiGe Fin formation technique using shallow trench isolation (STI) first or STI last strategy for the high mobility channel FinFET device is systematically investigated. A 20 nm width and 35 nm height high crystalline quality of the Si0.7Ge0.3 Fin formation for STI first scheme is demonstrated by utilizing a new developed Si Fin etching, Si Fin recess and SiGe selective epitaxial growth process. For the STI last strategy, a novel chemical mechanical planarization (CMP) treated three-layer SiGe strain relaxed buffer (SRB) is successfully fabricated and a 50 nm high crystal quality and atomically smooth surface Si0.5Ge0.5 layer on this SRB is attained. Moreover, a spike annealing is employed to avoid the Si0.5Ge0.5 Fin oxidation during STI densification with an acceptable STI etching rate. However, both a spike annealing and a lower temperature of traditional furnace at 850 °C or 750 °C suffer micro-trench issue during the Fin reveal process. Therefore, a new developed process, named as STI recess first, is developed to resolve both thermal instability and micro-trench issue at the same time. A minor Si0.5Ge0.5 Fin loss with a sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for STI last scheme is realized by utilizing this new developed STI recess first process.

(Invited) Ion Implantation and Activation of n- and p-Type Dopants in GaN

GaN-based power switching devices are of significant interest for high efficiency power conversion circuits in medium voltage applications. However, there are still significant challenges preventing mass production and widespread adoption. Recently, GaN-based vertical and lateral power devices have attracted significant interest due to promising device results coupled with progress in native substrate, epitaxial growth, and processing technology developments. However, there are two significant limiting factors for vertical GaN power devices at present. The first issue is substrate and epitaxial layer uniformity and reliability, and the second is the lack of a planar selective-area doping process. While p-type epitaxial growth capability and the ability to stack layers are quite mature from the LED industry, power devices require planar selective-area doping, which is a routine step by ion implantation in the Si and SiC device industry. The ability to implant and activate dopants, particularly p-type dopants, in GaN still remains a challenge as implant activation typically requires annealing at temperatures ~ 2/3 of the melting point, which is a region where the GaN crystal is unstable and readily decomposes to Ga + N2 at atmospheric pressure. The NRL-developed symmetric multicycle rapid thermal annealing (SMTRA) technique has been the most successful, demonstrating electrical activation of up to ~10% of the implanted Mg dopant atoms using a combination of a temporary, thermally stable capping layer, annealing in a moderate nitrogen overpressure, and performing a well-optimized annealing temperature profile including multiple spike anneals. Advances in the SMRTA process development, including optimization of capping processes, implantation profile, and processing steps such as metallization and surface treatments will be reviewed here. In addition, the evaluation of components of the SMRTA process, such as the cap and overpressure anneal, have been applied to Si implantation for n-type doping and will be presented here. This is a critical step to reduce contact resistance in lateral GaN structures as well as form the source regions of vertical devices that is typically accomplished by selective area regrowth. The use of ion implantation and activation utilizes fewer process steps and avoids impurity incorporation at sidewalls compared to the selective area regrowth process, and has been shown to yield lower contact resistance as well. This presentation will review advances in both Mg and Si ion implantation and assess the viability of this process for practical device fabrication.

Enhanced Thermal Stability of Low-k Ethyl-Bridged Organosilicas Using Laser Spike Annealing

Incorporating organic bridges within porous organosilica films is a promising route to achieving required mechanical properties of ultralow-k dielectric films. To retain these critical organic bridges during thermal processing, submillisecond laser spike annealing (LSA) of sol–gel-derived, low-k, ethyl-bridged organosilica films was investigated. Structural and dielectric properties changes, as a function of the peak annealing temperature between 400 and ∼1400 °C, were determined by using a lateral-gradient LSA technique. Under LSA, the ethyl-bridged structures were found to remain stable to the highest LSA peak temperatures; in contrast, nearly 40% of the bridges were lost by 540 °C under hot plate annealing. Refining of Si–O–Si structures, and porosity generation from remnant porogens, was found to begin above ∼700 °C with densification only occurring ∼350 °C higher. This ability of LSA to retain organic bridges within a silica network during thermal processing may ultimately enable development of high-...

Characterization of arsenic plasma doping and postimplant processing of silicon using medium energy ion scattering

Plasma doping (PLAD) is increasingly applied in microelectronic device manufacture to produce high throughput, high fluence implants. In this medium energy ion scattering (MEIS) study of the PLAD process, Si(100) wafers were exposed to an As containing plasma while pulse biased negatively to 7 kV to cause (recoil) implantation and deposition of As. Quantitative MEIS depth profiling analysis in conjunction with energy spectrum simulation was applied to characterize the near-surface layer changes of the Si wafer following (i) the PLAD process, (ii) two types of chemical wet clean (oxidizing and nonoxidizing), and (iii) spike annealing in an N2 atmosphere. MEIS analysis showed that the PLAD process produced an intermixed As/Si layer, with a near-surface As content of ∼40% that decayed almost linearly to near-zero at a depth of ∼17 nm. This mixed As/Si layer was unstable in air and the initially recorded 1.2 nm thick oxide cap layer grew over a period of four months to 3.5 nm with a concurrent 25% As loss by sublimation. The application of the industry standard, oxidizing wet chemical clean removed the top As and concurrently produced a ∼14 nm thick Si oxide above the remaining implanted As profile, which matched the tail of original As implant profile. As depth profiles measured for the 7 kV PLAD process after a wet clean and spike annealing showed solid phase epitaxial regrowth of the disordered layer. A detailed comparison of the random and aligned MEIS spectra yielded depth profiles of substitutional As with a concentration in excess of 1 × 1021 As cm−3 over a depth greater than 10 nm. The retained dose of 1.35 × 1015 cm−2 represents a ∼70% increase in substitutional As compared to that recorded after a nonoxidizing clean. Such an alternative wet chemical clean, in which Si reoxidation did not occur, was applied to determine the depth of the mixed As/Si layer removed. Found to be 7 nm, the analysis indicated that the etching process ceased when the Si concentration reached 4 × 1022 cm−3. After spike annealing, part of the remaining As had segregated in a thin layer under a 1.6 nm thick surface oxide. The retained As dose in this case was 8 × 1014 cm−2, equivalent to a 1% As substitutional dopant concentration to a depth of ∼14 nm. Different substitutional As doses measured with MEIS were found to correlate closely with sheet resistance measurements, confirming that equating the substitutional As with the active As dose remains correct for these ultrashallow profiles, typically 10 nm deep.

(Invited) Vertical GaN Devices Enabled By Selective Area P-Type Doping

A key element for enabling high performance vertical GaN power electronic devices is the capability to realize selective area p-type doping. The ability to arbitrarily define p-type regions through ion implantation eliminates the need for epitaxial regrowth on etched surfaces, which is currently a well-known technological roadblock. However, activation of implanted Mg is also a challenge, since activation of the Mg acceptors requires annealing at temperatures above the thermodynamic stability limits of GaN in atmosphere. Implementing the symmetric multi cycle rapid thermal annealing (SMTRA) technique has been shown to activate up to ~10% of the implanted Mg dopant atoms. This technique includes a temporary thermally stable capping layer, annealing in a nitrogen overpressure, and performing a well-optimized annealing temperature profile including multiple spike anneals. Vertical GaN junction barrier Schottky (JBS) diodes and Schottky barrier diodes (SBDs) with implanted junction termination extension (JTE) are demonstrated using the SMRTA process, as are process module development toward trench MOSFET devices.

Reduction in number of crystal defects in a p+Si diffusion layer by germanium and boron cryogenic implantation combined with sub-melt laser spike annealing

To reduce the number of crystal defects in a p+Si diffusion layer by a low-thermal-budget annealing process, we have examined crystal recovery in the amorphous layer formed by the cryogenic implantation of germanium and boron combined with sub-melt laser spike annealing (LSA). The cryogenic implantation at −150 °C is very effective in suppressing vacancy clustering, which is advantageous for rapid crystal recovery during annealing. The crystallinity after LSA is shown to be very high and comparable to that after rapid thermal annealing (RTA) owing to the cryogenic implantation, although LSA is a low-thermal-budget annealing process that can suppress boron diffusion effectively. It is also shown that in the p+Si diffusion layer, there is high contact resistance due to the incomplete formation of a metal silicide contact, which originates from insufficient outdiffusion of surface contaminants such as fluorine. To widely utilize the marked reduction in the number of crystal defects, sufficient removal of surface contaminants will be required in the low-thermal-budget process.

Determination of critical cooling rates in metallic glass forming alloy libraries through laser spike annealing

The glass forming ability (GFA) of metallic glasses (MGs) is quantified by the critical cooling rate (RC). Despite its key role in MG research, experimental challenges have limited measured RC to a minute fraction of known glass formers. We present a combinatorial approach to directly measure RC for large compositional ranges. This is realized through the use of compositionally-graded alloy libraries, which were photo-thermally heated by scanning laser spike annealing of an absorbing layer, then melted and cooled at various rates. Coupled with X-ray diffraction mapping, GFA is determined from direct RC measurements. We exemplify this technique for the Au-Cu-Si system, where we identify Au56Cu27Si17 as the alloy with the highest GFA. In general, this method enables measurements of RC over large compositional areas, which is powerful for materials discovery and, when correlating with chemistry and other properties, for a deeper understanding of MG formation.

Ultrafast Self-Assembly of Sub-10 nm Block Copolymer Nanostructures by Solvent-Free High-Temperature Laser Annealing.

Laser spike annealing was applied to PS-b-PDMS diblock copolymers to induce short-time (millisecond time scale), high-temperature (300 to 700 °C) microphase segregation and directed self-assembly of sub-10 nm features. Conditions were identified that enabled uniform microphase separation in the time frame of tens of milliseconds. Microphase ordering improved with increased temperature and annealing time, whereas phase separation contrast was lost for very short annealing times at high temperature. PMMA brush underlayers aided ordering under otherwise identical laser annealing conditions. Good long-range order for sub-10 nm cylinder morphology was achieved using graphoepitaxy coupled with a 20 ms dwell laser spike anneal above 440 °C.

Inkjet-Printed In-Ga-Zn Oxide Thin-Film Transistors with Laser Spike Annealing

Inkjet-printed In-Ga-Zn oxide (IGZO) thin-film transistors (TFTs) have been fabricated at low temperature using laser spike annealing (LSA) treatment. Coffee-ring effects during the printing process were eliminated to form uniform IGZO films by simply increasing the concentration of solute in the ink. The impact of LSA on the TFT performance was studied. The field-effect mobility, threshold voltage, and on/off current ratio were greatly influenced by the LSA treatment. With laser scanning at 1 mm/s for 40 times, the 30-nm-thick IGZO TFT baked at 200°C showed mobility of 1.5 cm2/V s, threshold voltage of −8.5 V, and on/off current ratio >106. Our findings demonstrate the feasibility of rapid LSA treatment of low-temperature inkjet-printed oxide semiconductor transistors, being comparable to those obtained by conventional high-temperature annealing.

Laser Spike Annealing for Shallow Junctions in Ge CMOS

An annealing method capable of forming highly activated shallow junctions in Ge CMOS is still lacking. For the first time, nonmelt submillisecond laser spike annealing (LSA) is demonstrated to achieve high activation level, excellent diffusion control, and resulting low contact resistivity for both n-type and p-type Ge junctions when using P and B as the dopants, respectively. The thermal stability of the junctions activated by LSA is investigated. In addition, our results on Ge junctions and contacts are benchmarked systematically against published results using sheet resistance-junction depth ( ${R}_{s}-{X}_{{\!{j}}}$ ) plots and contact resistivity-dopant concentration ( $\rho _{c}-{N}$ ) plots.