Low-Frequency Noise Analysis of the Optimized Post High-k Deposition Annealing in FinFET Technology

Abstract

The optimized postdeposition annealing (PDA) of the high- ${k}$ metal gate is investigated for 1/ ${f}$ noise performance improvement in FinFET technology by using spike annealing (SPA) and SPA-combined millisecond flash annealing (MFLA) treatment. It demonstrates that the additional MFLA can significantly reduce the 1/ ${f}$ noise without device performance degradation. Based on the low-frequency noise analysis, the reduced 1/ ${f}$ noise arises from the decrease in the density of interface traps ( ${D}_{\textit {it}}$ ) between Si-fin and interfacial layer (IL) that is prepared with $\text{O}_{{3}}$ -oxidation. Furthermore, the gate leakage is suppressed without equivalent oxide thickness (EOT) penalty, which is considered as the high- ${k}$ (HfO $_{{2}}{)}$ quality improvement from reducing oxygen vacancies and passivating the dangling bonds by forming a stronger Hf–N from additional MFLA.