SPICE Circuit Simulator Research Articles

Application of SPICE simulation to study WDM and SCM systems using EDFAs with chirping

The authors have proposed an equivalent electrical circuit model of erbium-doped fiber amplifiers (EDFAs), including the chirping effect for teaching or studying the distortions and performance of lightwave transmission systems. Through the aid of a SPICE circuit simulator, its validity is demonstrated by analyzing the cross modulations of an eight-channel wavelength division multiplexing system. The intermodulations in an amplitude modulation-subcarrier multiplexing (SCM) system are demonstrated. The channel-number dependence of the composite second-order distortion in a 42-channel SCM system is shown, and its applications to analyze other systems are also discussed.

Contact resistance extraction in pentacene thin film transistors

We report on the contact resistances for pentacene thin film transistors with two different designs: top and bottom contact configurations (referred to as TC and BC TFTs, respectively) for two different contact metals (gold and palladium). The extraction was done based on the dependencies of the channel resistances on the gate length and gate voltage. The extracted gold TC TFT contact resistance depends on V GS, but shows no dependence on the drain bias. The TC TFT contact resistance is comparable to or exceeds the channel resistance for channels shorter than approximately 10 μm. The contact resistance of BC TFTs depends both on gate and drain bias. We propose a circuit simulating the BC TFT contact resistance and verify the circuit applicability by extracting and comparing the TFT channel resistances at different drain voltages. Our results reveal an important role played by contact resistances and provide an accurate model of the contact phenomena suitable for implementation in Spice or other circuit simulators.

Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.

Improved methods for yield-optimization of digital logic

Yield optimization remains the primary device-level design task in digital superconductor electronics. We discuss yield-optimization in the context of our particular software implementation, Malt2, which interfaces to the circuit simulator Spice. This version contains significant improvements both to the numerical algorithms and in ease of use. Two special algorithms of yield-optimization are extant, both of which map out the multidimensional operating region of the circuit and center parameters within the operating region. We describe modifications to these methods that make them practical. The greatest improvement to usability is a new method of defining correct circuit operation; an envelope is defined around each Spice-generated waveform based on two parameters that describe acceptable time and level uncertainty. The envelope can be applied to arbitrary waveforms and can be represented graphically. The features and algorithms of Malt2 are illustrated with circuit examples. Finally, we describe the role of yield optimization within the larger context of a complete design methodology and tool set.

Internet as a new graphical user interface for the SPICE circuit simulator

The Spice Internet Package (SIP) was developed using an Internet browser as a platform-independent graphical user interface. The SIP application has many options that include simulation of SPICE files, graphical postprocessing data, and online editing of SPICE files. It can run remotely through a network on any operating system.

High-frequency SPICE model of anisotropic conductive film flip-chip interconnections based on a genetic algorithm

This paper firstly reports on the high-frequency SPICE model of the ACF flip-chip interconnections up to 13 GHz. The extraction process is based on an optimization procedure, called a genetic algorithm, which is known as a robust optimization tool. The proposed equivalent circuit model of the ACF interconnection can readily be used in SPICE circuit simulations for signal integrity analysis of high-frequency packages. Two different ACF interconnections were studied using the Au-coated polymer ball and Ni-filled ball. The extracted models of the two ACFs were found strongly dependent on not only size and rigidity of the conducting balls, but also on their magnetic permeability.

Electrical modeling of the chip scale ball grid array package at radio frequencies

The CSBGA package is targeted for the next generation of wireless systems, since this packaging technology occupies significantly less real estate than conventional packaging. The smaller packages not only accommodate the shrinking size of cellular phones but also contain lower parasitics, which reduces signal integrity losses. This innovative new software is targeted for the engineer who, at his desktop PC or workstation, can rapidly generate an accurate radio frequency (RF) electrical model of an entire Chip Scale BGA package. Program operation consists of entering the available data, and in just minutes, retrieving output that can be used in a SPICE circuit simulation. The focus of this work is on the frequency dependent parasitics in which the skin depth effects are modeled as additional circuit elements. Routines were developed to model the frequency dependant variable resistance and inductance with as few components as possible in order to reduce the complexity of the SPICE topology but still maintain accuracy. The program was designed to be fast and portable contrasting other methods of modeling in which such attributes were sacrificed for greater accuracy. Models of an entire 144 I/O package can be generated in less than 1min on a SUN Ultra1 workstation. The models generated are targeted for RF systems having a wide range of use across military and commercial electronics applications.

A study of diode protection for giant magnetoresistive recording heads

ESD testing of giant magnetoresistive (GMR) heads with diode protection is described. While the use of diodes did increase the magnetic and failure voltages of the GMR head, the magnetic failure voltage was increased much less than the resistance failure voltage. This results in an unfortunate side effect, which is to dramatically increase the range over which magnetic damage occurs without a corresponding resistance change. This problem was especially clear for the case of two diodes in series. The current flow through the GMR head and diode were measured and agreed with SPICE circuit simulation results. The difference between magnetic and resistance protection is due to the nonlinear clamping behavior of the diode. We conclude that serious magnetic damage will be the predominant failure signature for GMR heads with ESD protect diodes.

Improved global rational approximation macromodeling algorithm for networks characterized by frequency-sampled data

Recently, the demand for high-performance wireless designs has been increasing while simultaneously the speed of high-end digital designs have crossed over the gigahertz range. New simulation tools which accurately characterize high-frequency interconnects are needed. This paper presents improvements to a new macromodeling algorithm. The algorithm employs curve-fitting techniques to achieve a pole-residue approximation of the frequency-sampled network. The frequency sampled S-parameters or Y-parameters can be obtained from measurement or full-wave simulation to characterize the frequency-dependent interconnects behavior. The improvements extend the approach to lossless structures, increase its accuracy with pole-clustering, and ensure its validity with a passivity test. This paper addresses some of the special considerations that must be made to the method so it can efficiently and accurately be applied to lossless circuits and structures. The resulting algorithm is now capable of accurately extracting a wide-band frequency domain macromodel from frequency-sampled data for either LC circuit (lossless) or RLC circuits (lossy). The frequency-domain macromodel can be linked to a SPICE circuit simulator for mixed signal circuit analysis using RF, analog, and digital circuits. The circuit can be simulated in the time domain using recursive convolution.

Using Spice Circuit Simulation Program in Reliability Analysis of Redundant Systems with Non-Repairable Units and Common-Cause Failures

The effectiveness of Simulation Program with Integrated Circuit Emphasis (SPICE) in calculating probabilities, reliability, steady-state availability and mean-time to failure of redundant systems with non-repairable units and common-cause failures described by Markov models is demonstrated. General equations and procedure for constructing the equivalent circuit forNparallel units are presented. Results obtained, forN=1,2,3, using SPICE are compared with previously published results obtained using the Laplace transform method. Full SPICE listings are included.

Multiple operating points in a CMOS log-domain filter

A second order bandpass filter was designed by converting a conventional bipolar junction transistor-based log-domain filter circuit to its weak-inversion CMOS equivalent. When biased as designed, the filter performed as expected, but the integrated circuit at times self-biased to an unintended operating point, rendering the circuit useless. This behavior is related to the positive feedback loops used in log domain (and many other) circuits. Such situations cannot, in general, be predicted by inspection of the circuit topology. A method is presented for predicting and analyzing multiple operating points in SPICE circuit simulation. Of course, the method's predictions apply only to the circuit as modeled in the simulator. Detailed analysis illustrates that the number of operating points can depend on the modeling of effects (in this case, well-substrate leakage currents) that are often modeled carelessly, if at all.

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

Quasi-stationary analysis of the electric field in anisotropic laminated composites

This paper deals with the analysis of the quasistationary electric field in the presence of anisotropic laminated composites. Both cylindrical and box composite structures are examined in the two-dimensional domain. Two methods are proposed to solve the problem. The first is a numerical procedure employing the finite-difference time domain which uses a direct implicit scheme; the second is an equivalent circuit network which is solved by the use of the standard circuit simulator SPICE. For the composite box structure, the results obtained by means of the two approaches are compared; it is possible to observe a good agreement between them.

Reliability and Availability Analysis of Some Systems with Common-Cause Failures Using SPICE Circuit Simulation Program

The effectiveness of SPICE circuit simulation program in calculating probabilities, reliability, steady-state availability and mean-time to failure of repairable systems described by Markov models is demonstrated. Two examples are presented. The first example is a warm standby system with common-cause failures and human errors. The second example is a non-identical unit parallel system with common-cause failures. In both cases recourse to numerical solution is inevitable to obtain the Laplace transforms of the probabilities. Results obtained using SPICE are compared with previously published results obtained using the Laplace transform method. Full SPICE listings are included.

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design

The present state of the art in analytical MOSFET modeling for SPICE circuit simulation is reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulatio...

JSPICE: a component-based distributed Java front-end for SPICE

The design and implementation of a component-based distributed Java front-end for the Berkeley SPICE circuit-simulation program is described. The front-end is designed as a client–server application implemented via the Remote Method Invocation (RMI) API. A graphical user-interface is implemented on the client-side, which has multiple components for command and control, graphing, text-editing and communication with the server. JavaBeans API is used as the underlying component model. On the server side, the native SPICE code (in C language) is converted into a dynamic library and is interfaced with the Java Server code using Java Native Interface (JNI) API. Implementation issues related to modifications in the SPICE code enabling multiple invocations as a shared object, efficient input/output of simulation data from the Java code, waveform compression and extraction for display on the client-side, real-time transfer of SPICE generated runtime messages from the server to client etc. are discussed. Benchmark results comparing the performance of file input using various Java I/O classes are presented. © 1998 John Wiley & Sons, Ltd.

Failure mechanism and SPICE modeling of [formula omitted] HBT long-term current instability

The long-term current instability of AlGaAs GaAs heterojunction bipolar transistor (HBT) is studied, and the physical mechanism contributing to such a behavior is investigated. Based on this, a model capable of predicting the HBT long-term current drift and mean time to failure (MTTF) is developed. In addition, such a model is implemented into SPICE circuit simulator, thus allowing the simulation of HBT circuits subjected to an electrical and thermal stress condition.

Circuit analysis of BiCMOS gate delay

A circuit analysis of the BiCMOS switching transient is presented. The BiCMOS pull-up delay as a function of transistor parameters and power supply voltage is evaluated. The analytical predictions are compared with SPICE circuit simulation. Good agreement between the model and SPICE simulation is obtained. Twodimensional numerical device simulation is used to examine the physical insight into BiCMOS device operation.

A SPICE model for near-field transient analysis of ferromagnetic grids

Ferromagnetic grids are becoming more and more popular for electromagnetic shielding applications in avionics, satellite design, and power electronic systems. This paper presents an equivalent homogeneous but anisotropic model of a planar ferromagnetic grid. The nonlinear characteristic and the hysteresis of the material are taken into account. The field source is a low frequency magnetic dipole placed in the proximity of the grid. Both grid and source models are given in the form of multiconductor transmission line (TL) equations. They are solved, in the time domain, by the circuit simulator SPICE.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model.