Speedup Measurements Research Articles

Regulating Public Transit Networks: How do Urban-Intercity Diversification and Speed-up Measures Affect Firms' Cost Performance?

Empirical studies on the cost structure of Public Transit Networks are mainly based on specialized firms providing urban or intercity services. In this study we estimate a translogarithmic variable cost function to assess the behaviour of returns to scale and the impact of network characteristics. The analysis is based on a sample of 45 Italian municipal companies observed from 1996 to 1998 and including both specialized and mixed transit operators. Results confirm previous evidence on the existence of natural monopoly in the industry and support a regulation introducing competitive tenders to access to the market. In addition, we provide insights about the advantages associated with urban-intercity diversification and with the improvement of network commercial speed. Cost benefits can then be achieved by promoting mergers between neighbouring firms, so as to create new companies operating on integrated local networks and supplying in combination urban and intercity public transport. Implications of such a strategy for the design of tender mechanisms are also underlined, together with the need for a regulatory policy which takes more care of speed-up measures.

OdinMP/CCp?a portable implementation of OpenMP for C

We describe here the design and performance of OdinMP/CCp, which is a portable compiler for C-programs using the OpenMP directives for parallel processing with shared memory. OdinMP/CCp was written in Java for portability reasons and takes a C-program with OpenMP directives and produces a C-program for POSIX threads. We describe some of the ideas behind the design of OdinMP/CCp and show some performanceresults achieved on an SGI Origin 2000 and a Sun E10000. Speedup measurements relative to a sequential version of the test programs show that OpenMP programs using OdinMP/CCp exhibit excellent performance on the Sun E10000 and reasonable performance on the Origin 2000. Copyright © 2000 John Wiley & Sons, Ltd.

MAPPING PARALLEL ITERATIVE ALGORITHMS FOR PDE COMPUTATIONS ON A DISTRIBUTED MEMORY COMPUTER

This work deals with the investigation of the performance of parallel iterative algorithms, used for the solution of linear systems obtained from the discretization of Elliptic PDEs using the Finite Element Collocation method. To increase parallelicity the initial matrix is reordered and then the algorithm is mapped on a distributed memory parallel computer. The case of the Star architecture with master-slave communication of the processors is studied. Earlier work of the authors is improved here and at the same time a new solution approach is developed so that the application of these iterative algorithms on more general problems is feasible. Speedup, processor utilization and efficiency measures are presented. The theoretical optimum is almost reached even though fixed number of processors was available.

The M-cache: A message-handling mechanism for multicomputer systems

This paper presents the design and evaluation of the M-cache, a small, fast and intelligent memory for handling messages at the processing nodes of multicomputer systems. The M-cache is neither a conventional cache nor a message buffer, though it has some characteristics of both. It provides hardware support for the message search operation often performed in message-directed programming, a programming style inherent to the implementation of object-oriented paradigms on distributed computing systems. It also provides a mechanism for bandwidth matching between the interconnection network and local memory of a node. Through simulation experiments, we have studied the execution of concurrent algorithms on systems with and without M-caches to obtain relative speedup measures. The results show that a modest investment in silicon is sufficient to effect over an order of magnitude reduction in message-retrieval time. Such hardware support is needed to make the cost-effective implementation of fine-grain concurrent programs a reality.

Performance comparison of the CRAY-2 and CRAY X-MP/416 supercomputers

The serial and parallel performance of one of the world's fastest general purpose computers, the CRAY-2, is analyzed using the standard Los Alamos Benchmark Set plus codes adapted for parallel processing. For comparison, architectural and performance data are also given for the CRAY X-MP/416. Factors affecting performance, such as memory bandwidth, size and access speed of memory, and software exploitation of hardware, are examined. The parallel processing environments of both machines are evaluated, and speedup measurements for the parallel codes are given.

POSC—a partitioning and optimizing SISAL compiler

Single-assignment languages like SISAL offer parallelism at all levels—among arbitrary operations, conditionals, loop iterations, and function calls. All control and data dependencies are local, and can be easily determined from the program. Various studies of SISAL programs have shown that they contain massive amounts of potential parallelism . There are two major challenges in converting this potential parallelism into real speedup on multiprocessor systems. First, it is important to carefully select the useful parallelism in a SISAL program, so as to obtain good speedup by trading off parallelism with overhead. Second, it is important to do sequential optimizations , so that the sequential components (tasks) of the SISAL program have comparable execution times with sequential languages such as Fortran, Pascal and C. The POSC compiler system described in this paper addresses both issues by integrating previous work on efficient sequential implementation of SISAL programs with previous work on selecting the useful parallelism in a SISAL program. The combined approach is validated by real speedup measurements on a Sequent Balance multiprocessor.

Utilizing multidimensional loop parallelism on large scale parallel processor systems

Program parallelism and processor allocation issues for parallel processor systems are discussed. Optimal processor assignment algorithms are presented for simple and complex nested parallel loops. These processor assignment schemes can be used by the compiler to perform static processor allocation to multiply nested parallel loops. Speedup measurements for EISPACK and IEEE DSP subroutines that result from the optimal assignment of processors to parallel loops are also presented. These measurements indicate that optimal processor assignments result in almost linear speedups on parallel processor machines with a few tens of processes and significantly high speedups for machines with hundreds or thousands of processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance of symbolic applications on a parallel architecture

The results of a study of a family of parallel symbolic architectures executing several parallel applications are presented. The class of architectures being simulated is characterized by a shared memory structure, by a hierarchical interconnect, and by clustered processors. Speedup measurements were obtained from six different application kernels. Measurements were also performed to assess the degradation of speedup as a function of the interconnection delays, and to study the effect of different scheduling algorithms. The results presented support the claim that the proposed architecture would be a powerful parallel symbolic computation system. The paper discusses processor starvation, fine grain parallelism, unever loads, foreign reference, schedule and indeterminate computation with respect to the applications chosen.

Effectiveness Of Public Transport Priorisation

The paper aims at assessing urban transport policies to priorise public transport. A mathematical model is developed to optimise bus operating parameters (average fare, bus size and total bus-kms) under public road transport speed-up measures (bus lanes and signal priority) and car pricing (purchase and fuel taxes, road and parking pricing). The objective is the overall fuel consumption reduction on the road network. Experimentation on the case study of Rome shows negligible effects of policy based on bus operating parameters optimisation alone. This policy proves more effective when joined with car pricing than with public road transport speed-up measures. Optimal bus operating parameters are highly affected by relative sensitivity of bus demand to fare and time costs.