Runtime Speedup Research Articles

Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System

Massively parallel memory systems are designed to deliver high bandwidth at relatively low clock speed for memory-intensive applications implemented on programmable logic. For example, the Convey HC-1 provides 1,024 DRAM banks to each of four FPGAs through a full crossbar, presenting a peak bandwidth of 76.8GB/s to the user logic. Such highly parallel memory systems suffer from high latency, and their effective bandwidth is highly sensitive to access ordering. To achieve high performance, the user must use a customized memory interface that combines scheduling, latency hiding, and data reuse. In this article, we describe the design of a custom memory interface for 3D stencil kernels on the Convey HC-1 that incorporates these features. Experimental results show that the proposed memory interface achieves a speedup in runtime of 2.2 for 6-point stencil and 9.5 for 27-point stencil when compared to a naive memory interface.

DCEMRI.jl: a fast, validated, open source toolkit for dynamic contrast enhanced MRI analysis.

We present a fast, validated, open-source toolkit for processing dynamic contrast enhanced magnetic resonance imaging (DCE-MRI) data. We validate it against the Quantitative Imaging Biomarkers Alliance (QIBA) Standard and Extended Tofts-Kety phantoms and find near perfect recovery in the absence of noise, with an estimated 10–20× speedup in run time compared to existing tools. To explain the observed trends in the fitting errors, we present an argument about the conditioning of the Jacobian in the limit of small and large parameter values. We also demonstrate its use on an in vivo data set to measure performance on a realistic application. For a 192 × 192 breast image, we achieved run times of <1 s. Finally, we analyze run times scaling with problem size and find that the run time per voxel scales as O(N1.9), where N is the number of time points in the tissue concentration curve. DCEMRI.jl was much faster than any other analysis package tested and produced comparable accuracy, even in the presence of noise.

Constraint reduction procedures for reduced‐order subsurface flow models based on POD–TPWL

SummaryThe properties and numerical performance of reduced‐order models based on trajectory piecewise linearization (TPWL) and proper orthogonal decomposition (POD) are assessed. The target application is subsurface flow modeling, although our findings should be applicable to a range of problems. The errors arising at each step in the POD–TPWL procedure are described. The impact of constraint reduction on accuracy and stability is considered in detail. Constraint reduction entails projection of the overdetermined system into a low‐dimensional subspace, in which the system is solvable. Optimality conditions for constraint reduction, in terms of error minimization, are derived. Galerkin and Petrov–Galerkin projections are shown to correspond to optimality in norms that involve weighting with the Jacobian matrix. Two new treatments, inverse projection and weighted inverse projection, are suggested. These methods minimize error in appropriate norms, although they require substantial preprocessing computations. Numerical results are presented for oil reservoir simulation problems. Galerkin projection provides reasonable accuracy for simpler oil–water systems, although it becomes unstable in more challenging cases. Petrov–Galerkin projection is observed to behave stably in all cases considered. Weighted inverse projection also behaves stably, and it provides the highest accuracy. Runtime speedups of 150–400 are achieved using these POD–TPWL models. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation

Transient analysis of large-scale power delivery network (PDN) is a critical task to ensure the functional correctness and desired performance of today’s integrated circuits (ICs), especially if significant transient noises are induced by clock and/or power gating due to the utilization of extensive power management. In this paper, we propose an efficient algorithm for PDN transient analysis based on sparse approximation. The key idea is to exploit the fact that the transient response caused by clock/power gating is often localized and the voltages at many other “inactive” nodes are almost unchanged, thereby rendering a unique sparse structure. By taking advantage of the underlying sparsity of the solution structure, a modified conjugate gradient algorithm is developed and tuned to efficiently solve the PDN analysis problem with low computational cost. Our numerical experiments based on standard benchmarks demonstrate that the proposed transient analysis with sparse approximation offers up to $2.2\times $ runtime speedup over other traditional methods, while simultaneously achieving similar accuracy.

Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method

Statistical analysis of SRAM has emerged as a challenging issue because the SRAM cell failure probability is extremely small. In this paper, we develop a novel efficient sampling, searching and estimating method to capture the probability of SRAM failure. Particularly, we propose an innovative Adaptive Multi-Level Sliding-Window (AMLSW) method to find the failure boundary in the parameter space with less computational cost. The proposed AMLSW method applies an integrated optimization engine to adaptively explore the failure boundary by sampling a sequence of parameter points and calculating the simulation result in sliding windows. Its key features include ellipsoid transformation, multi-level grid partition and sliding window algorithm to make our method efficient and accurate for finding the SRAM failure probability and failure boundary in parameter space. Furthermore, we provide theoretical analysis on our new AMLSW method. The experimental results of a commercial 65nm SRAM cell demonstrate that the AMLSW method achieves 1.7–40× runtime speed-up over the existing methods without surrendering accuracy, and dramatically high speed-up over normal M-C sampling method. Moreover, this new method provides the failure boundary in the parameter space as shown in experiments.

A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding

As design-for-manufacturability techniques have become widely used to improve the yield of nano-scale semiconductor technology in recent years, hotspot detection methods have been investigated with a view to calibrating layout patterns that tend to reduce yield. In this paper, we propose two graph models, i.e., skeleton graph and space graph, to formulate polygon topology and spatial relationship among polygons. In addition, a Prüfer encoding-based method is presented to encode each skeleton graph. Single polygon matching problem is then equivalent to the verification of graph isomorphism, which is realized by checking the identity of two enhanced Prüfer codes associated with two skeleton graphs. A branch and bound-based pattern anchoring algorithm is presented to resolve the vertex ordering problem for isomorphism checking. The general exact pattern matching problem can then be accomplished by adopting the space graph to identify the similarity of spatial relationship among polygons. Vias are one of the most device components that attract much attention in monitoring manufacturing variation due to via alignment issue, but hotspot detection rarely takes vias into consideration. Multilayer hotspot detection can also be realized by extending the skeleton graph to maintain the relations between adjacent layers through vias. Experimental results show that we can achieve 5.6 × runtime speedup than design-rule-based methodology in average for single layer hotspot detection while the runtime for multilayer hotspot is roughly equal to the summation of that for individual single layer hotspot detection.

CloudFlow: A data-aware programming model for cloud workflow applications on modern HPC systems

Traditional High-Performance Computing (HPC) based big-data applications are usually constrained by having to move large amount of data to compute facilities for real-time processing purpose. Modern HPC systems, represented by High-Throughput Computing (HTC) and Many-Task Computing (MTC) platforms, on the other hand, intend to achieve the long-held dream of moving compute to data instead. This kind of data-aware scheduling, typically represented by Hadoop MapReduce, has been successfully implemented in its Map Phase, whereby each Map Task is sent out to the compute node where the corresponding input data chunk is located. However, Hadoop MapReduce limits itself to a one-map-to-one-reduce framework, leading to difficulties for handling complex logics, such as pipelines or workflows. Meanwhile, it lacks built-in support and optimization when the input datasets are shared among multiple applications and/or jobs. The performance can be improved significantly when the knowledge of the shared and frequently accessed data is taken into scheduling decisions.To enhance the capability of managing workflow in modern HPC system, this paper presents CloudFlow, a Hadoop MapReduce based programming model for cloud workflow applications. CloudFlow is built on top of MapReduce, which is proposed not only being data aware, but also shared-data aware. It identifies the most frequently shared data, from both task-level and job-level, replicates them to each compute node for data locality purposes. It also supports user-defined multiple Map- and Reduce functions, allowing users to orchestrate the required data-flow logic. Mathematically, we prove the correctness of the whole scheduling framework by performing theoretical analysis. Further more, experimental evaluation also shows that the execution runtime speedup exceeds 4X compared to traditional MapReduce implementation with a manageable time overhead.

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method

The development of emerging spin-transfer torque random access memory (STT-RAM) is facing two major technical challenges-poor write reliability and high write energy, both of which are severely impacted by process variations and thermal fluctuations. The evaluations on STT-RAM design metrics and robustness often require a hybrid simulation flow, i.e., modeling the CMOS and magnetic devices with SPICE and macro-magnetic models, respectively. Very often, such a hybrid simulation flow involves expensive Monte Carlo simulations when the design and behavioral variabilities of STT-RAM are taken into account. In this paper, we propose a fast and scalable semi-analytical method-PS3-RAM, enabling efficient statistical simulations in STT-RAM designs. By eliminating the costly macro-magnetic and SPICE simulations, PS3-RAM achieves more than 100\(000\boldsymbol {\times }\) runtime speedup with excellent agreement with the result of conventional simulation method. PS3-RAM can also accurately estimate the STT-RAM write error rate and write energy distributions at both magnetic tunneling junction switching directions under different temperatures, demonstrating great potential in the analysis of STT-RAM reliability and write energy at the early design stage of memory or micro-architecture.

IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs

Modern SRAM-based field-programmable gate arrays (FPGAs) are prone to single event upsets compared to application-specific integrated circuits. We propose a synthesis-based in-place x-filling algorithm by utilizing don't cares to augment the reliability of FPGA-based designs. Compared to circuit- and architecture-based solutions, our algorithm is in place, and does not incur area, power, performance, and design time overheads. Compared to other synthesis-based algorithms, we take into account widely accepted interconnect architecture. For the 10 largest combinational MCNC benchmark circuits mapped to 6-LUT architecture, our approach achieves up to 37% greater failure rate reduction, and up to 7 × runtime speedup, compared to the best known synthesis-based in-place algorithm, namely the in-place decomposition algorithm.

Energy efficient adaptive clustering of on-chip power delivery systems

Efficient on-chip power delivery is a significant design challenge in heterogeneous real time systems with multiple power domains. The power efficiency of the overall heterogeneous power delivery system has recently been shown to be a strong function of the clustering of the power supplies – the specific configuration in which the power converters and regulators are co-designed. A recursive clustering algorithm with polynomial computational complexity is proposed for a dynamically controllable power distribution system. The algorithm is evaluated on IBM power grid benchmark circuits, yielding up to a 21% increase in power efficiency, and orders of magnitude speedup in runtime.

EPIQ-efficient detection of SNP-SNP epistatic interactions for quantitative traits.

Motivation: Gene–gene interactions are of potential biological and medical interest, as they can shed light on both the inheritance mechanism of a trait and on the underlying biological mechanisms. Evidence of epistatic interactions has been reported in both humans and other organisms. Unlike single-locus genome-wide association studies (GWAS), which proved efficient in detecting numerous genetic loci related with various traits, interaction-based GWAS have so far produced very few reproducible discoveries. Such studies introduce a great computational and statistical burden by necessitating a large number of hypotheses to be tested including all pairs of single nucleotide polymorphisms (SNPs). Thus, many software tools have been developed for interaction-based case–control studies, some leading to reliable discoveries. For quantitative data, on the other hand, only a handful of tools exist, and the computational burden is still substantial.Results: We present an efficient algorithm for detecting epistasis in quantitative GWAS, achieving a substantial runtime speedup by avoiding the need to exhaustively test all SNP pairs using metric embedding and random projections. Unlike previous metric embedding methods for case–control studies, we introduce a new embedding, where each SNP is mapped to two Euclidean spaces. We implemented our method in a tool named EPIQ (EPIstasis detection for Quantitative GWAS), and we show by simulations that EPIQ requires hours of processing time where other methods require days and sometimes weeks. Applying our method to a dataset from the Ludwigshafen risk and cardiovascular health study, we discovered a pair of SNPs with a near-significant interaction (P = 2.2 × 10−13), in only 1.5 h on 10 processors.Availability: https://github.com/yaarasegre/EPIQContact: heran@post.tau.ac.il

Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

3-D many-core processor (3-D MCP) has become an emerging technology to tackle the power wall problem due to rapidly increasing number of transistors. However, when maximizing the throughput of 3-D MCP, which is expressed as a weighted sum of the speeds, due to the inherent heat removal limitation, thermal issues must be taken into consideration. Since the temperature of a core strongly depends on its location in the 3-D IC, a proper task allocation can alleviate the thermal problem and improve the throughput. Nevertheless, conventional techniques require computationally intensive thermal simulation, which prohibits its usage from the online application. In this paper, we propose an efficient online task allocation and task migration algorithm attempting to maximize the throughput of 3-D MCP simultaneously, considering unfinished tasks left from the last scheduling interval and new incoming tasks of this scheduling interval. The results of our experiments show that our proposed method achieves a 20.82X runtime speedup. These results are comparable to the exhaustive solutions obtained from optimization-modeling software LINGO. In addition, on average, our throughput results, with and without consideration of unfinished tasks, are only 4.39% and 0.69% worse, respectively, than that of the exhaustive method. In 128 task-to-core allocations, our method takes only 0.951 ms, which is 59.39 times faster than that of the previous work.

The positive edge criterion within COIN-OR׳s CLP

This paper presents the first direct implementation of the positive edge criterion using COIN-OR׳s CLP, where it has been combined with the Devex pivot rule. Positive edge is designed to take advantage of degeneracy in linear programming. The original implementation, while yielding strong computational results, suffers from significant overhead caused by CPLEX not allowing modification of its standard pivot rules. We test the method over the same set of highly degenerate problems used by the original authors of positive edge. To test its robustness, we solve a set of linear problems from Mittelmann׳s library which contains instances with a wide range of degeneracy levels. These computational results show that below a degeneracy level of 25%, the positive edge criterion is on average neutral while above this threshold, it reaches an average run time speedup of 2.3, with a maximum at 4.2 on an instance with a 75% degeneracy level.

Reduced-Order Modeling for Compositional Simulation by Use of Trajectory Piecewise Linearization

Summary Compositional simulation can be very demanding computationally as a result of the potentially large number of system unknowns and the intrinsic nonlinearity of typical problems. In this work, we develop a reduced-order modeling procedure for compositional simulation. The technique combines trajectory piecewise linearization (TPWL) and proper orthogonal decomposition (POD) to provide a highly efficient surrogate model. The compositional POD-TPWL method expresses new solutions in terms of linearizations around states generated (and saved) during previously simulated “training” runs. High-dimensional states are projected (optimally) into a low-dimensional subspace by use of POD. The compositional POD-TPWL model is based on a molar formulation that uses pressure and overall component mole fractions as the primary unknowns. Several new POD-TPWL treatments, including the use of a Petrov-Galerkin projection to reduce the number of equations (rather than the Galerkin projection, which was applied previously), and a new procedure for determining which saved state to use for linearization are incorporated into the method. Results are presented for heterogeneous 3D reservoir models containing oil and gas phases with up to six hydrocarbon components. Reasonably close agreement between full-order reference solutions and compositional POD-TPWL simulations is demonstrated for the cases considered. Construction of the POD-TPWL model requires preprocessing overhead computations equivalent to approximately three or four full-order runs. Runtime speedups by use of POD-TPWL are, however, very significant—up to a factor of 800 for the cases considered. The POD-TPWL model is thus well suited for use in computational optimization, in which many simulations must be performed, and we present an example demonstrating its application for such a problem.

Fast and scalable parallel layout decomposition in double patterning lithography

For 32/22nm technology nodes and below, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising and show the presented parallel layout decomposition methods obtain upto 21× speedup in runtime and upto 7.5×reduction in peak memory consumption with acceptable solution quality.

Reduced-order modeling for thermal recovery processes

Thermal recovery can entail considerably higher costs than conventional oil recovery, so the use of computational optimization techniques in designing and operating these processes may be beneficial. Optimization, however, requires many simulations, which results in substantial computational cost. Here, we implement a model-order reduction technique that aims at large reductions in computational requirements. The technique considered, trajectory piecewise linearization (TPWL), entails the representation of new solutions in terms of linearizations around previously simulated (and saved) training solutions. The linearized representation is projected into a low-dimensional space, with the projection matrix constructed through proper orthogonal decomposition of solution “snapshots” generated in the training step. Two idealized problems are considered here: primary production of oil driven by downhole heaters and a simplified model for steam-assisted gravity drainage, where water and steam are treated as a single “effective” phase. The strong temperature dependence of oil viscosity is included in both cases. TPWL results for these systems demonstrate that the method can provide accurate predictions relative to full-order reference solutions. Observed runtime speedups are very substantial, over 2 orders of magnitude for the cases considered. The overhead associated with TPWL model construction is equivalent to the computation time for several full-order simulations (the precise overhead depends on the number of training runs), so the method is only applicable if many simulations are to be performed.

Mapping a Jacobi Iterative Solver onto a High-Performance Heterogeneous Computer

High-performance heterogeneous computers that employ field programmable gate arrays (FPGAs) as computational elements are known as high-performance reconfigurable computers (HPRCs). For floating-point applications, these FPGA-based processors must satisfy a variety of heuristics and rules of thumb to achieve a speedup compared with their software counterparts. By way of a simple sparse matrix Jacobi iterative solver, this paper illustrates some of the issues associated with mapping floating-point kernels onto HPRCs. The Jacobi method was chosen based on heuristics developed from earlier research. Furthermore, Jacobi is relatively easy to understand, yet is complex enough to illustrate the mapping issues. This paper is not trying to demonstrate the speedup of a particular application nor is it suggesting that Jacobi is the best way to solve equations. The results demonstrate a nearly threefold wall clock runtime speedup when compared with a software implementation. A formal analysis shows that these results are reasonable. The purpose of this paper is to illuminate the challenging floating-point mapping process while simultaneously showing that such mappings can result in significant speedups. The ideas revealed by research such as this have already been and should continue to be used to facilitate a more automated mapping process.

Efficient SRAM Failure Rate Prediction via Gibbs Sampling

Statistical analysis of SRAM has emerged as a challenging issue because the failure rate of SRAM cells is extremely small. In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells. In particular, we adapt the Gibbs sampling technique from the statistics community to find the optimal probability distribution for importance sampling with a low computational cost (i.e., a small number of transistor-level simulations). The proposed Gibbs sampling method applies an integrated optimization engine to adaptively explore the failure region in a Cartesian or spherical coordinate system by sampling a sequence of 1-D probability distributions. Several implementation issues such as 1-D random sampling and starting point selection are carefully studied to make the Gibbs sampling method efficient and accurate for SRAM failure rate prediction. Our experimental results of a 90 nm SRAM cell demonstrate that the proposed Gibbs sampling method achieves 1.4-4.9× runtime speedup over other state-of-the-art techniques when a high prediction accuracy is required (e.g., the relative error defined by the 99% confidence interval reaches 5%). In addition, we further demonstrate an important example for which the proposed Gibbs sampling algorithm accurately estimates the correct failure probability, while the traditional techniques fail to work.

Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers

Codes that have large-stride/irregular-stride (L/I) memory access patterns, e.g., sparse matrix and linked list codes, often perform poorly on mainstream clusters because of the general purpose processor (GPP) memory hierarchy. High performance reconfigurable computers (HPRC) contain both GPPs and field programmable gate arrays (FPGAs) connected via a high-speed network. In this research, simple 64-bit floating-point codes are used to illustrate the runtime performance impact of L/I memory accesses in both software-only and FPGA-augmented codes and to assess the benefits of mapping L/I-type codes onto HPRCs. The experiments documented herein reveal that large-stride software-only codes experience severe performance degradation. In contrast, large-stride FPGA-augmented codes experience minimal performance degradation. For experiments with large data sizes, the unit-stride FPGA-augmented code ran about two times slower than software. On the other hand, the large-stride FPGA-augmented code ran faster than software for all the larger data sizes. The largest showed a 17-fold runtime speedup.

Spinning fast iterative data flows

Parallel dataflow systems are a central part of most analytic pipelines for big data. The iterative nature of many analysis and machine learning algorithms, however, is still a challenge for current systems. While certain types of bulk iterative algorithms are supported by novel dataflow frameworks, these systems cannot exploit computational dependencies present in many algorithms, such as graph algorithms. As a result, these algorithms are inefficiently executed and have led to specialized systems based on other paradigms, such as message passing or shared memory. We propose a method to integrate incremental iterations , a form of workset iterations, with parallel dataflows. After showing how to integrate bulk iterations into a dataflow system and its optimizer, we present an extension to the programming model for incremental iterations. The extension alleviates for the lack of mutable state in dataflows and allows for exploiting the sparse computational dependencies inherent in many iterative algorithms. The evaluation of a prototypical implementation shows that those aspects lead to up to two orders of magnitude speedup in algorithm runtime, when exploited. In our experiments, the improved dataflow system is highly competitive with specialized systems while maintaining a transparent and unified dataflow abstraction.