Speed Field Programmable Gate Array Research Articles

A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree

Binarized neural networks (BNNs) and batch normalization (BN) have already become typical techniques in artificial intelligence today. Unfortunately, the massive accumulation and multiplication in BNN models bring challenges to field-programmable gate array (FPGA) implementations, because complex arithmetics in BN consume too much computing resources. To relax FPGA resource limitations and speed up the computing process, we propose a BNN accelerator architecture based on consolidation compressed tree scheme by combining both XNOR and accumulation operation of the low bit into a systematic one. During the compression process, we adopt 0-padding (not ±1) to achieve no-accuracy-loss from software modeling to hardware implementation. Moreover, we introduce shift-addition-BN free binarization technique to shorten the delay path and optimize on-chip storage. To sum up, we drastically cut down the hardware consumption while maintaining great speed performance with the same model complexity as the previous design. We evaluate our accelerator on MNIST and CIFAR-10 dataset and implement the whole system on the ARTIX-7 100T FPGA with speed performance of 2052.65 GOP/s and area efficiency of 70.15 GOPS/KLUT.

A digital force-to-rebalance scheme for high-frequency bulk-acoustic-wave micro-gyroscopes

This paper presents a digital force-to-rebalance (FTR) control system to substantially extend the bandwidth of high-Q mode-matched high-frequency micro-electro-mechanical systems (MEMS) bulk-acoustic-wave (BAW) gyroscopes. Principle and challenges for the FTR operation of high-frequency mode-matched MEMS gyroscopes are studied and a digital implementation is demonstrated based on high speed field programmable gate arrays (FPGA) using a 4.2 MHz silicon BAW gyroscope with a Q of 144,000. By using a properly designed cascaded lead controller, the bandwidth of the mode-matched gyroscope is extended from 14 Hz to 180 Hz with no degradation in angle random walk (ARW) and an improved long-term bias stability, which will allow high-Q mode-matched gyroscopes to be used for advanced high-bandwidth high-dynamic-range applications.

Design of an Industrial IoT-Based Monitoring System for Power Substations

The Internet of Things (IoT) concept allows objects to share data through wired or wireless connections for communication purposes. The industrial Internet of Things (IIoT) is an extended concept of IoT that refers to an integration of data acquisition, communication, and processing on a real-time network. Currently, IIoT has been involved with the development of smart grids in many applications. As the operation of power systems is extremely time-critical, low-latency communication needs to be considered for most control and monitoring applications. Real-time capability of IoT is considered as a key feature for monitoring and control applications of power systems. Therefore, system operators can use the real-time monitoring system to provide better decisions for both technical- and financial-related matters. In this article, a high-speed IIoT-based monitoring system with recording functions is developed and implemented for a power system substation. Due to the high reliability and processing speed of field-programmable gate arrays (FPGAs), an FPGA-embedded controller is adopted in this system. The IoT platform also provides remote visualization for system operators in real-time. This article mainly aims to provide a practical application that was implemented and tested in a real-power substation. The system incorporates the features of an IoT platform with the needs of high-speed real-time applications while using a single high-resolution time source as the reference for both steady-state and transient conditions.

High Performance Reversible Direct Data Synthesizer for Radio Frequency Applications

Design of Reversible logic gate enabled Reconfigurable Direct digital synthesizer is evaluated here. The need for Direct Digital Synthesizers (DDS) inherently finds application in the area of radio frequency communication. DDS is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. The proposed design presents an important analysis based on Reversible logic gates for the application of DDS which is a powerful device employed to produce standard signal sweeps from lowest frequency to highest frequency. The sweeps of DDS frequency depends on the configurable frequency words produced by high speed Field Programmable Gate Array (FPGA) platforms. Because operations within DDS devices are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power. Here the proposed system focuses on development of DDS through Artificial Intelligence (AI) with Field Programmable Gate Array (FPGA) devices. The primary need for FPGA and AI combination provides the replacement of analog Phase Locked Loop (PLL) in traditional DDS circuits. The fully digital architecture enable the system able to configure the digital PLL developed inside the FPGA core. Low noise and Low power factor is being achieved through low power techniques utilized in the architecture development part. The proposed system increase the sweep frequency resolution, Reverse fluctuations through leakage voltage etc.

Silicon Photonics towards Disaggregation of Resources in Data Centers

In this paper, we demonstrate two subsystems based on Silicon Photonics, towards meeting the network requirements imposed by disaggregation of resources in Data Centers. The first one utilizes a 4 × 4 Silicon photonics switching matrix, employing Mach Zehnder Interferometers (MZIs) with Electro-Optical phase shifters, directly controlled by a high speed Field Programmable Gate Array (FPGA) board for the successful implementation of a Bloom-Filter (BF)-label forwarding scheme. The FPGA is responsible for extracting the BF-label from the incoming optical packets, carrying out the BF-based forwarding function, determining the appropriate switching state and generating the corresponding control signals towards conveying incoming packets to the desired output port of the matrix. The BF-label based packet forwarding scheme allows rapid reconfiguration of the optical switch, while at the same time reduces the memory requirements of the node’s lookup table. Successful operation for 10 Gb/s data packets is reported for a 1 × 4 routing layout. The second subsystem utilizes three integrated spiral waveguides, with record-high 2.6 ns/mm2, delay versus footprint efficiency, along with two Semiconductor Optical Amplifier Mach-Zehnder Interferometer (SOA-MZI) wavelength converters, to construct a variable optical buffer and a Time Slot Interchange module. Error-free on-chip variable delay buffering from 6.5 ns up to 17.2 ns and successful timeslot interchanging for 10 Gb/s optical packets are presented.

Optically-Enabled Bloom Filter Label Forwarding Using a Silicon Photonic Switching Matrix

Simplified forwarding schemes relying on Bloom filter (BF)-based labels emerge as a promising approach for coping with the substantial increase in lookup table memory requirements associated with the growing number of end-hosts in DataCenters. In this paper, we present for the first time the successful implementation of a BF-label forwarding scheme over a silicon photonic switch fabric and we demonstrate its functionality with 10 Gb/s data packets that carry BF-encoded labels. The optically enabled BF-label forwarding setup utilizes a Si-based 4 × 4 electro-optic switch directly controlled by an amplifier-less and digital-to-analog-converter-less high speed Field Programmable Gate Array board. The FPGA is responsible for extracting the BF-label from the incoming packets and for carrying out the BF-based forwarding function, determining the appropriate switching state towards conveying incoming packets to the desired output. The use of BF-label forwarding allows for rapid switch reconfiguration avoiding the need for large look-up table updates as the network topology changes and devices are added, removed or simply change physical location. Successful operation for 10 Gb/s data packets has been obtained for a 1 × 4 routing layout.

The implementation of real-time plasma electron density calculations on EAST

The plasma electron density is one of the most fundamental parameters in tokamak experiment. It is widely used in the plasma control system (PCS) real-time control, as well as plasma physics analysis. The 3-wave polarimeter-interferometer (POINT) system had been used to measure the plasma electron density on the EAST since last campaign. This paper will give the way to realize the real-time measurement of plasma electron density.All intermediate frequency (IF) signals after POINT system, in the 0.5–3MHz range, stream to the real-time density calculation system (DCS) to extract the phase shift information. All the prototype hardware is based on NI Flex RIO device which contains a high speed Field Programmable Gate Array (FPGA). The original signals are sampled at 10M Samples/s, and the data after roll-over module are transmitted to PCS by reflective memory (RFM). With this method, real-time plasma electron density data with high accuracy and low noise had been obtained in the latest EAST tokamak experiment.

Design of PXI Digital Storage Oscilloscope Module Based on FPGA

A digital storage oscilloscope module in automatic test equipment was designed based on PIX bus. The field programmable gate array (FPGA) is used as the logic control unit. The circuit of high speed ADC and FPGA interface, clock management, and high speed data access were designed based on hardware modules. The digital storage oscilloscope module was successfully applied to the practical test system, whose performance was good, stable, and achieved the desired design goals.

English

Binary phase shift keying (BPSK) and quadrature phase shift Keying (QPSK)modulation techniques are often proposed for satellite communications and band-limited communication channels; however, both modulations are important in high speed data communications. High speed data communications are implemented on high speed hardware in wireless systems. The paper presents the design of a QPSK and BPSK digital communication modulators and their implementations on high speed field-programmable gate array (FPGA) using Quartus II. Also, for these modulation schemes, resource utilization was introduced. Both modulations were designed in Quartus II using VHDL hardware description language. It was shown that transmission of QPSK modulator is fast than transmission of BPSK modulator at the same bit error performance. According to BPSK, QPSK modulator uses more memory. But other resources equal to for these modulation. Principles of the BPSK modulation and QPSK modulation are illustrated using schematic diagrams. The analysis of theoretical aspects of the BPSK and QPSK modulations are represented. Both modulations waveforms are illustrated using a simulation program. Implementations of the BPSK and QPSK systems on FPGA are shown using algorithms of modulator. Key words: Binary phase shift keying (BPSK), quadrature phase shift Keying (QPSK), field-programmable gate array (FPGA).

PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations

Field programmable gate arrays (FPGAs) are widely used in applications where online reconfigurable signal processing is required. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nanoscale. As these transistors reduce in size intrinsic variability becomes more of a problem and to reliably create electronic designs according to specification time consuming statistical simulations become necessary; and even with accurate models and statistical simulation, the fabrication yield will decrease as every physical instance of a design behaves differently. This paper describes an adaptive, evolvable architecture that allows for correction and optimization of circuits directly in hardware using bioinspired techniques. Similar to FPGAs, the programmable analog and digital array (PAnDA) architecture introduced provides a digital configuration layer for circuit design. Accessing additional configuration options of the underlying analog layer enables continuous adjustment of circuit characteristics at runtime, which enables dynamic optimization of the mapped design's performance. Moreover, the yield of devices can be improved postfabrication via reconfiguration of the analog layer, which can overcome faults induced due to variability and process defects. Since optimization goals are generic, i.e., not restricted to reducing stochastic variability, power consumption or increasing speed, the same mechanisms can also enhance the device's fault tolerant abilities in the case of component degradation and failures during its lifetime or when exposed to hazardous environments.

A Switching Control Strategy for the Reduction of Torque Ripple for PMSM

This paper proposes the field-programmable gate array (FPGA) implementation of a variable structure system predictive sequential switching control strategy, as applied to a permanent magnet synchronous machine. In the case of ac motor drives, in contrast to conventional vector control where the inverter is not taken into consideration by the controller, the proposed control integrates the inverter model and the inverter states. It allows obtaining faster torque dynamics than vector control algorithms. The main design specifications are a reduced switching frequency and simple hardware implementation. A predictive sliding mode controller has been developed, designed as finite-state machine, and implemented with a FPGA. This new logic FPGA torque and speed controller has been developed, analyzed, and experimentally verified.

FPGA-Based Predictive Sliding Mode Controller of a Three-Phase Inverter

This paper proposed a novel predictive variable-structure-switching-based current controller for a three-phase load driven by a power inverter. The design specifications are robustness to load electrical parameters, fast dynamic response, reduced switching frequency, and simple hardware implementation. In order to meet previous specifications, a sliding mode controller has been developed, which is designed as finite-state automata, and implemented with a field-programmable gate array (FPGA) device. The switching strategy implemented within the state transition diagram provides for a minimum number of switches by the three-phase inverter that is confirmed through simulation and experimental results. Its regulation using the proposed control law provides good transient response by the brushless ac motor control. However, this does not limit the wider applicability of the proposed controller that is suitable for different types of ac loads (rectifier and inverter) and ac motors (induction, synchronous, and reluctance). A new logical FPGA torque and speed controller is developed, analyzed, and experimentally verified.

CRionScan: A stand-alone real time controller designed to perform ion beam imaging, dose controlled irradiation and proton beam writing

High resolution ion microbeams, usually used to perform elemental mapping, low dose targeted irradiation or ion beam lithography needs a very flexible beam control system. For this purpose, we have developed a dedicated system (called “CRionScan”), on the AIFIRA facility (Applications Interdisciplinaires des Faisceaux d’Ions en Région Aquitaine). It consists of a stand-alone real-time scanning and imaging instrument based on a Compact Reconfigurable Input/Output (Compact RIO) device from National Instruments™. It is based on a real-time controller, a Field Programmable Gate Array (FPGA), input/output modules and Ethernet connectivity. We have implemented a fast and deterministic beam scanning system interfaced with our commercial data acquisition system without any hardware development. CRionScan is built under LabVIEW™ and has been used on AIFIRA’s nanobeam line since 2009 (Barberet et al., 2009, 2011) [1,2]. A Graphical User Interface (GUI) embedded in the Compact RIO as a web page is used to control the scanning parameters. In addition, a fast electrostatic beam blanking trigger has been included in the FPGA and high speed counters (15MHz) have been implemented to perform dose controlled irradiation and on-line images on the GUI. Analog to Digital converters are used for the beam current measurement and in the near future for secondary electrons imaging. Other functionalities have been integrated in this controller like LED lighting using Pulse Width Modulation and a “NIM Wilkinson ADC” data acquisition.