Spatial Parallelism Research Articles

Optical supercomputing: introduction to special issue

Optical computers use photons rather than electrons to represent and modify information. Computer architectures that are based on optics offer several interesting features: • Current architectures use energy to move electrons while photons move by nature. Thus, an optical information processing devices, consisting of passive components, may not use energy. Transport of information is accomplished with high speed and exceptional good efficiency and without crosstalk. • Transmission of information over long distances is done by using light transmitted in fiber optics. Thus, there exists an inherent bottleneck of light to electronics conversion when information processing is done by electrons. • High spatial parallelism. • High density of information represented in 3D (holography) using free space or crystals. • Some specific information tasks are already naturally solved by optical devices.

A modern solver interface to manage solution algorithms in the Community Earth System Model

Global Earth System Models (ESMs) can now produce simulations that resolve ~50 km features and include finer scale, interacting physical processes. However, the current explicit algorithms that dominate production ESMs require ever-decreasing time steps in order to achieve these fine-resolution solutions, which limits time to solution even when efficiently exploiting the spatial parallelism. Solution methods that overcome these bottlenecks can be quite intricate, and there is no single set of algorithms that perform well across the range of problems of interest. This creates significant implementation challenges, which is further compounded by the complexity of ESMs. Therefore, prototyping and evaluating new algorithms in these models requires a software interface that is flexible, extensible, and easily introduced into the existing software. We describe our efforts to create a parallel solver interface that links the Trilinos collection of solver libraries to the Glimmer Community Ice Sheet Model (Glimmer-CISM), a continental ice-sheet model used in the Community Earth System Model (CESM). We demonstrate this interface within both current and developmental versions of Glimmer-CISM and provide strategies for its integration into the rest of the CESM.

Redundancy Mining for Soft Error Detection in Multicore Processors

The trends in technology scaling and the reduction in supply voltages have significantly improved the performance and energy consumption in modern microprocessors. Microprocessors are being built with higher degrees of spatial parallelism and deeper pipelines to improve performance, which, however, makes them more susceptible to transient faults. Radiation causes "transient faults” or "single-event transients” in logic, which, once propagated and latched, become full cycle errors or soft errors. If radiation hits memory elements, this is usually called an "single-event upset” or "soft error” as it can further propagate as a full cycle error. The problem of soft errors is further exacerbated in large multiprocessors employed in servers in which reliability is a key concern. In the past, the technique of lockstep execution of the original and the duplicate instructions has been used for error detection in multiprocessors. However, the execution of redundant threads in the on-chip multiprocessor (CMP) provides error detection at lower overheads, since the branch outcomes of the leading thread can be exploited during the execution of the trailing thread, and also because the interprocessor communication latency is a key concern for lockstepping. In this paper, we show that by mining various redundancies inherent within a single core, the interprocessor communication can be brought down to a minimum. Toward this, we propose techniques based on 1) temporal redundancy, 2) data value redundancy, and 3) information redundancy for error detection in multicore designs. We exploit temporal redundancy by using the "latency slack cycles” (LSC) of an instruction, which we define as the number of cycles before the computed result from the instruction becomes the source operand of a subsequent instruction. The value-based detection technique is explored by exploiting the width of the operands with small data values and information redundancy is exploited by the generation of residue code check bits for the source operands. We show that with a clustered core multiprocessor, the interprocessor communication overhead can be significantly reduced. In our proposed multicore design, when a soft error is detected, error correction is achieved by rolling back the execution to a previous checkpoint state and re-executing the instructions. The proposed techniques have been implemented on the RSIM simulation framework and validated using the SPLASH benchmarks. Experimental results indicate that the soft error detection schemes proposed in this work, can be implemented, on the average, with less than 10 percent increase in CPI on modern multicore designs.

Rebuilding Iberian motorways with slime mould

Abstract Plasmodium of a cellular slime mould Physarum polycephalum is a unique living substrate proved to be efficient in solving many computational problems with natural spatial parallelism. The plasmodium solves a problem represented by a configuration of source of nutrients by building an efficient foraging and intra-cellular transportation network. The transportation networks developed by the plasmodium are similar to transport networks built by social insects and simulated trails in multi-agent societies. In the paper we are attempting to answer the question “How close plasmodium of P. polycephalum approximates man-made motorway networks in Spain and Portugal, and what are the differences between existing motorway structure and plasmodium network of protoplasmic tubes?”. We cut agar plates in a shape of Iberian peninsula, place oat flakes at the sites of major urban areas and analyse the foraging network developed. We compare the plasmodium network with principle motorways and also analyse man-made and plasmodium networks in a framework of planar proximity graphs.

Cellular Automata Simulations on a FPGA cluster

The emergence of multicore architectures and the chip industry’s plan to roll out hundreds of cores per die sometime in the near future might have triggered the evolution of von Neumann architectures towards a parallel processing paradigm. The capability to have hundreds of cores per die is exciting, but how optimally we are able to utilize such a resource remains a challenge. Since there are no straightforward solutions we seek inspiration from relevant scientific processes. Cellular automata which are inherently decentralized and spatially extended structures provide a potential candidate among parallel processing alternatives. The availability of spatial parallelism on field programmable gate arrays make them the ideal platform to investigate cellular automata systems as potential parallel processing paradigms on multicore architectures. This article presents a massively parallel implementation for a floating-point-based cellular automata using special purpose hardware such as Field Programmable Gate Array (FPGAs). The challenge is to best map an application to the underlying many-core architecture and address issues such as inter-core communication, scalability, and flexibility both in terms of hardware and software. Maxwell — a 64-node FPGA supercomputer, is used for accelerator implementations that range from a single to a multiple FPGA-enabled system. A performance model is proposed and demonstrated to closely reproduce measured execution times. The performance model enables identification of the main sources of overhead and suggests improvements to the architecture and implementation of the lattice Boltzmann method and compute-bound cellular automata in general. Further, a 2 million cell 2DQ9 lattice Boltzmann method lattice with periodic boundary conditions, simulated using a multiple FPGA chip accelerator implementation, is presented. The performance model shows how the FPGA-enabled PC cluster is the preferred multiple FPGA organization over the multiple FPGA-based PC setup. Latency hiding is fully exploited for PC cluster-based system implementations and demonstrated using system profiling.

A Reconfigurable Architecture for Rotation Invariant Multi-View Face Detection Based on a Novel Two-Stage Boosting Method

We present a reconfigurable architecture model for rotation invariant multi-view face detection based on a novel two-stage boosting method. A tree-structured detector hierarchy is designed to organize multiple detector nodes identifying pose ranges of faces. We propose a boosting algorithm for training the detector nodes. The strong classifier in each detector node is composed of multiple novelly designed two-stage weak classifiers. With a shared output space of multicomponents vector, each detector node deals with the multidimensional binary classification problems. The design of the hardware architecture which fully exploits the spatial and temporal parallelism is introduced in detail. We also study the reconfiguration of the architecture for finding an appropriate tradeoff among the hardware implementation cost, the detection accuracy, and speed. Experiments on FPGA show that high accuracy and marvelous speed are achieved compared with previous related works. The execution time speedups range from 14.68 to 20.86 for images with size of 160×120 up to 800×600 when our FPGA design (98 MHz) is compared with software solution on PC (Pentium 4 2.8 GHz).

Exploring parallel capabilities of an innovative numerical method for recovering image velocity vectors field

In this paper an efficient method devoted to estimate the velocity vectors field is investigated. The method is based on a quasi-interpolant operator and involves a large amount of computation. The operations characterizing the computational scheme are ideal for parallel processing because they are local, regular and repetitive. Therefore, the spatial parallelism of the process is studied to rapidly proceed in the computation on distributed multiprocessor systems. The process has shown to be synchronous, with good task balancing and requiring a small amount of data transfer.

Placing pipeline stages on a Grid: Single path and multipath pipeline execution

In a Grid computing environment, several applications such as scientific data analysis and visualization are naturally computation and communication intensive. These applications can be decomposed into a sequence of pipeline stages which can be placed on different Grid nodes for concurrent execution. Due to the aggregation of the computation and communication costs involved, finding the way to place such pipeline stages on a Grid in order to achieve the maximum application throughput becomes a challenging problem. This paper proposes a solution that considers both the pipeline placement and the data movement between stages. Specifically, we try to minimize the computation cost of the pipeline stages while preventing the communication overhead between successive stages from dominating the entire processing time. Our proposed solution consists of two novel methods. The first method is single path pipeline execution, which exploits only temporal parallelism, and the second method is multipath pipeline execution, which considers both temporal and spatial parallelism inherent in any pipeline applications. We evaluate our work in a simulated environment and also conduct a set of experiments in a real Grid computing system. When compared with the results from several traditional placement methods, our proposed methods give the highest throughput.

Effect of loading on the organization of the collagen fibril network in juvenile equine articular cartilage

We investigated the effects of exercise-induced loading on the collagen network of equine articular cartilage. Collagen fibril architecture at a site (1) subjected to intermittent high-intensity loading was compared with that of an adjacent site (2) sustaining continuous low-level load. From horses exposed to forced exercise (CONDEX group) or not (PASTEX group), the spatial parallelism of fibrils and the orientation angle between fibrils and the surface at depths 9 microm apart through cartilage from surface to tidemark were determined using polarized light microscopy, and expressed as parallelism index (PI) and orientation index (OI). PI was significantly higher in site 2 than 1 in CONDEX and PASTEX groups. PI was significantly higher in forced exercised horses at site 2 but not site 1. OI was significantly greater (more perpendicular to the surface) in the superficial and deep cartilage of site 2 than 1 in both CONDEX and PASTEX groups. Superficial zone OI was higher in exercised horses at site 1 but not at site 2. Exercise increased collagen parallelism and affected orientation. The site differences in OI indicate that Benninghoff's classic predominantly perpendicular arcades appear not to be a consistent architectural feature, but adapt to local forces sustained.

Pipelining saturated accumulation

Aggressive pipelining and spatial parallelism allow integrated circuits (e.g., custom VLSI, ASICs, and FPGAs) to achieve high throughput on many digital signal processing applications. However, cyclic data dependencies in the computation can limit parallelism and reduce the efficiency and speed of an implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280 MHz on a Xilinx Spartan-3(XC3S-5000-4) FPGA, the maximum frequency supported by the component's DCM.

Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system

There are many design challenges in the hardware-software co-design approach for performance improvement of data-intensive streaming applications with a general-purpose microprocessor and a hardware accelerator. These design challenges are mainly to prevent hardware area fragmentation to increase resource utilization, to reduce hardware reconfiguration cost and to partition and schedule the tasks between the microprocessor and the hardware accelerator efficiently for performance improvement and power savings of the applications. In this paper a modular and block based hardware configuration architecture named memory-aware run-time reconfigurable embedded system (MARTRES) is proposed for efficient resource management and performance improvement of streaming applications. Subsequently we design a task placement algorithm named hierarchical best fit ascending (HBFA) algorithm to prove that MARTRES configuration architecture is very efficient in increased resource utilization and flexible in task mapping and power savings. The time complexity of HBFA algorithm is reduced to O( n) compared to traditional Best Fit (BF) algorithm’s time complexity of O( n 2), when the quality of the placement solution by HBFA is better than that of BF algorithm. Finally we design an efficient task partitioning and scheduling algorithm named balanced partitioned and placement-aware partitioning and scheduling algorithm (BPASA). In BPASA we exploit the temporal parallelism in streaming applications to reduce reconfiguration cost of the hardware, while keeping in mind the required throughput of the output data. We balance the exploitation of spatial parallelism and temporal parallelism in streaming applications by considering the reconfiguration cost vs. the data transfer cost. The scheduler refers to the HBFA placement algorithm to check whether contiguous area on FPGA is available before scheduling the task for HW or for SW.

FREQUENCY-MULTIPLEXING ABILITY OF COMPLEX-VALUED HEBBIAN LEARNING IN LOGIC GATES

Lightwave has attractive characteristics such as spatial parallelism, temporal rapidity in signal processing, and frequency band vastness. In particular, the vast carrier frequency bandwidth promises novel information processing. In this paper, we propose a novel optical logic gate that learns multiple functions at frequencies different from one another, and analyze the frequency-domain multiplexing ability in the learning based on complex-valued Hebbian rule. We evaluate the averaged error function values in the learning process and the error probabilities in the realized logic functions. We investigate optimal learning parameters as well as performance dependence on the number of learning iterations and the number of parallel paths per neuron. Results show a trade-off among the learning parameters such as learning time constant and learning gain. We also find that when we prepare 10 optical path differences and conduct 200 learning iterations, the error probability completely decreases to zero in a three-function multiplexing case. However, at the same time, the error probability is tolerant of the path number. That is, even if the path number is reduced by half, error probability is found almost zero. The results can be useful to determine neural parameters for future optical neural network systems and devices that utilize the vast frequency bandwidth for frequency-domain multiplexing.

Broadband analog to digital conversion with spatial-spectral holography

A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization.

Vision Chip Architecture for Detecting Line of Sight Including Saccade

Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.

Modular and distributed forward dynamic simulation of constrained mechanical systems – A comparative study

In this paper, we examine the modular development of two alternate methods for distributed computation of the forward dynamics simulations of constrained mechanical systems. We exploit the natural spatial parallelism of closed-chain linkages, initially, for the modular development of overall dynamics, and subsequently, for the distributed numerical simulation of the dynamics. Traditionally, the numerical simulation problem of constrained mechanical systems has been treated as two separate stages: the problem of algorithm development and the subsequent numerical problem of advancing the discretized differential equations in time. However the potential numerical instabilities arising from the formulation stiffness of the algorithm development stage has the potential to hinder the subsequent numerical integration stage. These aspects are also explored during the evaluation of the two alternative approaches for the distributed forward dynamics simulation of a four-bar linkage. A series of tests were performed on a real-time synchronized distributed computational system (RT-LAB) to evaluate the performance of both methods of simulation and preliminary results to quantify the overall computational efficiency and accuracy are presented.

Stream computations organized for reconfigurable execution

Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the flexibility and adaptability characteristic of software. While reconfigurable systems create new opportunities for engineering and delivering high-performance programmable systems, the traditional approaches to programming and managing computations used for hardware systems (e.g., Verilog, VHDL) and software systems (e.g., C, Fortran, Java) are inappropriate and inadequate for exploiting reconfigurable platforms. To address this need, we develop a stream-oriented compute model, system architecture, and execution patterns which can capture and exploit the parallelism of spatial computations while simultaneously abstracting software applications from hardware details (e.g., timing, device capacity, and microarchitectural implementation details) and consequently allowing applications to scale to exploit newer, larger, and faster hardware platforms. Further, we describe hardware and software techniques that make this late-bound platform mapping viable and efficient.

Modular and Recursive Kinematics and Dynamics for Parallel Manipulators

Constrained multibody systems typically feature multiple closed kinematic loops that con- strain the relative motions and forces within the system. Typically, such systems possess far more ar- ticulated degrees-of-freedom (within the chains) than overall end-effector degrees-of-freedom. Thus, actuation of a subset of the articulations creates mixture of active and passive joints within the chain. The presence of such passive joints interferes with the effective modular formulation of the dynamic equations-of-motion in terms of a minimal set of actuator coordinates as well the subsequent recursive solution for both forward and inverse dynamics applications. Thus, in this paper, we examine the development of modular and recursive formulations of equations-of-motion in terms of a minimal set of actuated-joint-coordinates for an exactly-actuated parallel manipulators. The 3 RRR planar parallel manipulator, selected to serve as a case-study, is an illustrative example of a multi-loop, multi-degree-of-freedom system with mixtures of ac- tive/passive joints. The concept of decoupled natural orthogonal complement (DeNOC) is combined with the spatial parallelism inherent in parallel mechanisms to develop a dynamics formulation that is both recursive and modular. An algorithmic approach to the development of both forward and inverse dynamics is highlighted. The presented simulation studies highlight the overall good nu- merical behavior of the developed formulation, both in terms of accuracy and lack of formulation stiffness.

Performance of local search heuristics on scheduling a class of pipelined multiprocessor tasks

This paper presents the evaluation of the solution quality of heuristic algorithms developed for scheduling multiprocessor tasks for a class of multiprocessor architectures designed to exploit temporal and spatial parallelism simultaneously. More specifically, we deal with multi-level or partitionable architectures where MIMD parallelism and multiprogramming support are the two main characteristics of the system. We investigate scheduling a number of pipelined multiprocessor tasks with arbitrary processing times and arbitrary processor requirements in this system. The scheduling problem consists of two interrelated sub-problems, which are finding a sequence of pipelined multiprocessor tasks on a processor and finding a proper mapping of tasks to the processors that are already being sequenced. For the solution of the second problem, various techniques are available. However, the problem remains of generating a feasible sequence for the pipelined operations. We employed three well-known local search heuristic algorithms that are known to be robust methods applicable to various optimization problems. These are Simulated Annealing, Tabu Search, and Genetic Algorithms. We then conduct computational experiments and evaluate the reduction achieved in completion time by each heuristic. We have also compared the results with well-known simple list-based heuristics.

A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities

The most obvious architectural solution for high-speed fuzzy inference is to exploit the temporal parallelism and spatial parallelism inherited in a fuzzy inference execution. However, the active rules in a fuzzy inference execution are often only a small part of the total rules. In this paper, we present a new architecture, which uses less hardware resources by discarding non-active rules in the earlier pipeline stage. Implementation data demonstrates that the proposed architecture achieves very good results in terms of the inference speed and the chip area.

Recursive Kinematics and Inverse Dynamics for a Planar 3R Parallel Manipulator

Abstract We focus on the development of modular and recursive formulations for the inverse dynamics of parallel architecture manipulators in this paper. The modular formulation of mathematical models is attractive especially when existing sub-models may be assembled to create different topologies, e.g., cooperative robotic systems. Recursive algorithms are desirable from the viewpoint of simplicity and uniformity of computation. However, the prominent features of parallel architecture manipulators-the multiple closed kinematic loops, varying locations of actuation together with mixtures of active and passive joints-have traditionally hindered the formulation of modular and recursive algorithms. In this paper, the concept of the decoupled natural orthogonal complement (DeNOC) is combined with the spatial parallelism of the robots of interest to develop an inverse dynamics algorithm which is both recursive and modular. The various formulation stages in this process are highlighted using the illustrative example of a 3R Planar Parallel Manipulator.