Space-time Mapping Research Articles

Designing Lower-Dimensional Regular Arrays for Algorithms with Uniform Dependencies

In this paper, we will propose a polynomial-time method to designm-dimensional regular arrays forn(n≥m+ 1) dimensional algorithms with uniform dependencies, regular algorithms. The proposed method has two steps: the first one is to transform an independently partitioned regular algorithm to a new one, which has an identity dependence matrix. We call this stepidentity transformation, which is an affine one. In the second step, we propose a spacetime mapping in a fixed form to map the new regular algorithm to a lower-dimensional regular array. Thus, anaffine spacetime mappingis constructed by combining the identity transformation and the fixed form's spacetime mapping together. With the proposed affine spacetime mapping, the original regular algorithm can be mapped to a lower-dimensional regular array in polynomial time, which depends only on the number of dimensions of the regular algorithm. Meanwhile, the designed regular array is asymptotically optimal in time and space.

Preconditioning index set transformations for time-optimal affine scheduling

Many regular algorithms, suitable for VLSI implementation, are naturally described by sets of integer index vectors together with a rule that assigns a computation to each vector. Regular VLSI structures for such algorithms can be found by mapping the index vectors to a discrete space-time with integer coordinates. If the scope is restricted to linear or affine mappings, then the minimization of the execution time for the VLSI implementation with respect to the space-time mapping is essentially an integer linear programming (ILP) problem. If the entries in the vector describing the time function must be integers, ILP techniques can be applied directly. There are, however, index sets that allow space-time mappings with rational, nonintegral entries. In such cases, ILP will not consider all possible affine time functions and an optimal solution may go unnoticed. In this paper we give sufficient conditions on the index set for when only integer time functions are allowed. We also give a general algorithm to find a "preconditioning" affine transformation of the index set, such that the transformed index set allows only integer time functions. ILP methods can then be used to find time-optimal architectures for the transformed algorithm. This considerably extends the class of algorithms for which time-optimal VLSI structures can be found.

A communication scheme for the distributed execution of loop nests withwhile loops

The mathematical model for the parallelization, or “space-time mapping,” of loop nests is the polyhedron model. The presence ofwhile loops in the nest complicates matters for two reasons: (1) the parallelized loop nest does not correspond to a polyhedron but instead to a subset that resembles a (multidimensional) comb and (2) it is not clear when the entire loop nest has terminated. We describe a communication scheme which can deal with both problems and which can be added to the parallel target loop nest by a compiler.

Closed-form mapping conditions for the synthesis of linear processor arrays

This paper addresses the problem of mapping algorithms with constant data dependences to linear processor arrays. The closed-form necessary and sufficient mapping conditions are derived to identify mappings without computational conflicts and data link collisions. These mapping conditions depend on the space-time mapping matrix and the problem size parameters only. Their correctness can be verified in constant time that is independent of problem size. The design of optimal linear processor arrays is formulated as a mathematic programming problem, which can be solved efficiently by a systematic enumeration of a polynomial search space.

One-dimensional processor arrays for linear algebraic problems

Using isomorphic embedding of the original dependence graphs in another graph before its space-time mapping onto array architectures, two linear processor arrays are designed for the Gauss-Jordan algorithm with partial pivoting and Cholesky decomposition. Each of these arrays comprises only (n+1)/2 processing elements (PEs), where n is the number of columns in the input matrices. The block pipelining period is n(n-1) cycles for the first array and n(n+1)/2 cycles for the second. If the matrices are processed sequentially, systems of linear equations are solved by the Gauss-Jordan algorithm with almost full processor utilisation, whereas for the Cholesky decomposition the utilisation of PEs is approximately two-thirds.

Determining objective functions in systolic array designs

The space-time mapping of the dependency matrix of an algorithm may be used to study proposed systolic array implementations. In this paper we consider nested loop structures and use the space-time mapping approach to examine six objective functions, processor pipelining rate, computation time, throughput, number of processing elements, geometric area and space utilization. An elementary expression for each of these objective functions is derived which depends only on the space-time transformation and the size of loops. Moreover, several necessary and sufficient conditions for optimizing an individual objective function are provided. >

Fault-tolerant design methodology for systolic array architectures

A systematic approach to the design of fault-tolerant VLSI systolic arrays is proposed. The approach comprises three steps. First, redundancies are introduced at the computation level by deriving different versions of the computation structure. This involves the modification of the dependency matrix (D) of an algorithm to reflect a given fault-tolerance requirement. Second, the dependency matrix of the respective version is mapped into arbitrarily large size VLSI systolic arrays, using space-time (S-T) mapping techniques. Finally, a fault-tolerant (FT) systolic array is constructed by merging the corresponding systolic array of the different versions of the computation. The scheme is applicable to any systolic array implementation and suitable for VLSI technology. The method is illustrated using the matrix multiplication algorithm.

A cost-optimal systolic algorithm for generating subsets

Subset generation, generating all 2 n − 1 subsets of an n-element set, is frequently necessary in combinatorial algorithms. In this paper, we shall utilize Moldovan's space-time mapping methodology to design a systolic algorithm for the subset generation problem. The algorithm is a cost-optimal design and can generate all subsets in lexicographic order. Since it can be run on a simple linear systolic array, it is amenable to VLSI implementation.

A systematic approach for designing concurrent error-detecting systolic arrays using redundancy

A systematic approach for designing systolic arrays with concurrent error detection (CED) capability using time and/or space redundancy is proposed. This approach is based on a new theory which relates CED and the generalized space-time mapping. Under a restriction that there is one generated (modified) variable in the systolic arrays, a simplified CED scheme is presented. That not only significantly reduces the hardware and time overheads but also has capability of error correction. As well, the resulting systolic array can be used to compute two problem instances simultaneously to achieve double throughput without extra cost.

Synthesis aspects in the design of efficient processor arrays from affine recurrence equations

Efficient implementation of problems on processor arrays requires dedicated compiling techniques. This paper proposes synthesis techniques in the design of processor array architectures from system of affine recurrence equations. They implement the spacetime mapping which determine the scheduling of the calculations and the allocation of these calculations to a surface of processors. The paper emphazises the two-steps space mapping which is composed of a classical linear allocation followed by the application of two specific partitioning techniques. These techniques reduce the number of processors and therefore result in more efficient parallel solutions. The paper is illustrated with the Cholesky factorization.

Space—time mapping, latency of data flow and concurrent error detection in systolic arrays

The problem of mapping a general iterative algorithm with nonunit increment/decrement steps of the loop indices onto a systolic array using space-time transformation is studied. Necessary and sufficient conditions for the existence of such a space-time mapping are presented. The latency of a systolic computation is characterised in terms of the space—time mapping and the increment/decrement step size of the iterative algorithm. Formulas for the latency of linear and 2D systolic arrays are derived. An efficient space—time mapping using restricted row operations which guarantees unit latency, thereby maximising the utilisation of the processors, is also proposed. Necessary and sufficient conditions under which column operations can be used to derive a legitimate space—time mapping are presented. A theory relating concurrent error detection and space—time mapping in systolic arrays is proposed. Based on this theory, existing (ad hoc) concurrent error detection approaches can be explained.

Systematic design of systolic arrays for computing multiple problem instances

The one-to-one space-time mapping approach has been extended to mapping multiple problem instances onto a single systolic array. Compared with previous methods, the proposed approach significantly reduces the number of I/O pins on the chip as well as increases the throughput and the ratio of throughput over space.

The synthesis of control signals for one-dimensional systolic arrays

This paper presents a method for the synthesis of control signals for one-dimensional systolic arrays from a program expressed as a set of uniform recurrence equations ( source UREs). The basic idea underlying the synthesis of control signals is to distinguish different types of computation prescribed by the source UREs with another set of uniform recurrence equations ( control UREs). To obtain one-dimensional systolic arrays with a description of both data and control signals, one simply applies the standard space-time mapping technique to the source and control UREs.

SPECIFYING CONTROL SIGNALS FOR SYSTOLIC ARRAYS BY UNIFORM RECURRENCE EQUATIONS

Starting with a system of uniform recurrence equations (source UREs) for a systolic design, we provide a method that allows a specification of control signals by another system of UREs (control UREs), which has no notion of time and space. Necessary and sufficient conditions for the correctness of the control UREs are stated. The standard space-time mapping technique is extended so that systolic arrays with a description of both data and control flow are directly synthesised from the source and control UREs. Optimisations of control signals are discussed. An example is provided.

Mapping in Inertial Frames

World space mapping in inertial frames is used to examine the Lorentz covariance of symmetry operations. It is found that the Galilean invariant concepts of simultaneity (S), parity (P), and time reversal symmetry (T) are not Lorentz covariant concepts for inertial observers. That is, just as the concept of simultaneity has no significance independent of the Lorentz inertial frame, likewise so are the concepts of parity and time reversal. However, the world parity (W) (i.e., the space-time reversal symmetry (P-T)) is a truly Lorentz covariant concept. Indeed, it is shown that only those mapping matrices M that commute with the Lorentz transformation matrix L (i.e., (M,L) = 0) are the ones that correspond to manifestly Lorentz covariant operations. This result is in accordance with the spirit of the world space Mach's principle. Since the Lorentz transformation is an orthogonal transformation while the Galilean transformation is not an orthogonal transformation, the formal relativistic space-time mapping theory used here does not have a corresponding non-relativistic counterpart. 12 refs.

Preliminary Study of Lightning Location Relative to Storm Structure

Lightning is being studied relative to storm structure using a VHP space-time discharge mapping system, radar, a cloud-to-ground flash locator, acoustic reconstruction of thunder, and other instrumentation. The horizontal discharge processes within the cloud generally propagate at speeds of 10-10 m/s. We have found horizontal extents of lightning up to 90 km. In an analysis of a limited number of flashes, lightning occured in or near regions of high cyclonic shear. Positive cloud-to-ground flashes have been observed emanating from several identifiable regions of severe storms. Lightning echoes observed with 10-cm radar are generally 10-25 dB greater than the largest precipitation echo in the storm.