South Pacific Design Automation Conference Research Articles

Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024)

Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024)

29th Asia and South Pacific Design Automation Conference

29th Asia and South Pacific Design Automation Conference

ASP-DAC2024: The 29th Asia and South Pacific Design Automation Conference

ASP-DAC2024: The 29th Asia and South Pacific Design Automation Conference

28th Asia and South Pacific Design Automation Conference

28th Asia and South Pacific Design Automation Conference

Report on the 28th Asia and South Pacific Design Automation Conference

The 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023) was held at Miraikan, National Museum of Emerging Science and Innovation, Tokyo, Japan, 16 char6319 January 2023. ASP-DAC, started in 1995, is a high-quality and premium conference on Electronic Design Automation (EDA) like other sister conferences such as Design Automation Conference (DAC); Design, Automation Test in Europe (DATE); International Conference on Computer Aided Design (ICCAD); and Embedded Systems Week (ESWEEK). ASP-DAC 2023 adopted an in-person conference style with online features which is the first time in ASP-DAC. Even though the last two ASP-DAC conferences were held as virtual conferences due to the COVID-19 pandemic, ASPDAC 2023 provided opportunities for face-to-face communication not only at sessions, but also at coffee breaks, banquet, and so on for in-person attendees. Online access mainly for participants who were difficult to physically attend was also provided as much as possible.

ASP-DAC 2023 : The 28th Asia and South Pacific Design Automation Conference

ASP-DAC 2023 : The 28th Asia and South Pacific Design Automation Conference

26th Asia and South Pacific Design Automation Conference

26th Asia and South Pacific Design Automation Conference

25th Asia and South Pacific Design Automation Conference

25th Asia and South Pacific Design Automation Conference

Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference

The 24th Asia and South Pacific Design Automation Conference (ASP-DAC) was held at Miraikan, National Museum of Emerging Science and Innovation, Tokyo, Japan, on 21–24 January 2019. ASP-DAC is a high-quality, premium conference in the electronic design automation (EDA) area, like other sister conferences such as the Design Automation Conference (DAC); Design, Automation, & Test in Europe (DATE); the International Conference on Computer Aided Design (ICCAD); and Embedded Systems Week (ESWEEK). ASP-DAC started in 1995 and has continuously offered the opportunity to know the recent advanced technologies on IC chip design and design automation areas, as well as to enable communication between researchers and designers around Asia and the South Pacific regions. As the first event in Tokyo, 346 researchers from 22 countries gathered not only from Asia and the South Pacific region but also from North America and Europe.

24th Asia and South Pacific Design Automation Conference

24th Asia and South Pacific Design Automation Conference

Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

The 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) was held at the International Convention Center, Jeju Island, South Korea, on 22–25 January 2018. ASP-DAC was founded in 1995 and has continuously offered opportunity for the researchers around Asia and South Pacific regions to communicate with each other and to get exposed to the advanced and recent technologies. This year’s event was sponsored by ACM Special Interest Group on Design Automation (SIGDA), the IEEE Circuits and Systems Society, and the IEEE Council on Electronic Design Automation. We also had two Japanese organizations, Institute of Electronics, Information and Communication Engineers and Information Processing Society of Japan, which supported the conference. We were very fortunate to have a number of corporate sponsors including Cadence, SK Hynix, Mentor, Synopsys, Entasys, Baum, and Silvaco. The conference was attended by 373 people, which is similar to when the conference was held in Chiba, Japan, last year; the largest number of attendees was from South Korea, followed by the United States, Taiwan, China, Japan, Hong Kong, and Germany.

Recap of the 22nd Asia and South- Pacific Design Automation Conference

The 22nd Asia and South-Pacific Design Automation Conference (ASP-DAC2017) was held at Makuhari Messe, Chiba (near Tokyo), Japan, from January 16 to 19, 2017. Makuhari Messe is one of the biggest international convention complexes in Japan and a memorable place where the first ASP-DAC was held in 1995.

The Analysis and Building of LibGALS System

The paper has been removed due to plagiarism. The original paper by Wei-Tsun Sun, Zoran Salcic and Avinash Malik can be found: “LibGALS: A Library for GALS Systems Design and Modeling” by Wei-Tsun Sun, Zoran Salcic and Avinash Malik published at 15th Asia South Pacific Design Automation Conference, Taipei, 18-21 Jan, 2010, pp. 107-112, doi 10.1109/ASPDAC.2010.5419912, published by ACM and IEEE.

Development of a large word-width high-speed asynchronous multiply and accumulate unit

This paper details the design of the fastest known asynchronous Multiply and Accumulate unit (MAC) architecture published to date. The MAC architecture herein is based on the MAC developed in Smith et al. (J. Syst. Archit. 47/12 (2002) 977–998). However, the MAC developed in Smith et al. (2002) contains conditional rounding, scaling, and saturation (CRSS) logic, not present in other comparable MACs (Twenty-Sixth Hawaii International Conference on System Sciences, vol. 1, 1993, pp. 379–388; Asian South-Pacific Design Automation Conference, 2000, pp. 15–16; Sixth IEEE International Conference on Proceedings of ICECS, vol. 2, 1999, pp. 629–633); thus making the comparison between the MAC developed in Smith et al. (2002) and other delay-insensitive/self-timed MACs in the literature not completely fair, in favor of the other MACs. This paper first details the removal of the CRSS logic from the MAC developed in Smith et al. (2002), and describes its subsequent optimal re-pipelining, in order to provide a more fair comparison. This yields a speedup of 1.12. Secondly, this paper details the application of the NULL Cycle Reduction technique (The 10th International Workshop on Logic and Synthesis, 2001, pp. 185–189; Gate and throughput optimizations for NULL convention self-timed digital circuits, Ph.D. Dissertation, School of Electrical Engineering and Computer Science, University of Central Florida, 2001) to the MAC's feedback loop, and subsequent re-pipelining of the feed-forward partial product generation and summation circuitry to further increase throughput, resulting in an additional speedup of 1.31 (a speedup of 1.46 over the MAC from Smith et al. (2002). Lastly, the bit-wise completion strategy is utilized in lieu of full-word completion to decrease the area required by 6% and also increase the MAC's throughput an additional 1%.