Source-gated Transistors Research Articles

(Invited) Organic Source-Gated Transistors for High-Gain Sensor Signal Conditioning

A set of important developments have been recently demonstrated in contact-controlled thin-film transistors [1-3] realized with organic semiconductors.Targeted at obtaining superior power efficiency, layout utilization and signal integrity, these advances largely focus on the electrical and geometrical optimization of the source area. Field-relief structures embedded into the source contact produce high intrinsic gain in both n-type and p-type inkjet-printed organic source-gated transistors (SGTs) [4-5], toward achieving the potential of such devices in high gain unipolar amplifiers [6]. Thermal effects are reduced via contact barrier – semiconductor interplay [7] and robust optical sensing of blue light is demonstrated [8]. Finally, utilizing the source barrier, as opposed the W/L geometry of the transistor to dictate drain current magnitude leads to compact and practical CMOS inverters when p-type DNTT-based organic SGTs are paired with n-type IGZO SGTs [9].By judicious and application-driven design (Figure 1) [10], the source-gated transistor and its evolution, the multimodal transistor [11], are showing significant potential in signal conditioning and sensing applications.[1] J. M. Shannon et al., IEEE Trans. Electron Devices, 60, 2444–2449 (2013).[2] A. Valletta et al., J. Appl. Phys. 114 064501 (2013).[3] J. Zhang, et al., PNAS 116, 4843 (2019).[4] Y. Hemmi, et al., Nanomaterials, 12, 4441 (2022).[5] Y. Hemmi, et al., Adv. Electron. Mater., 9, 2201263 (2023).[6] E. Bestelink, et al., IEEE Sens. J., 20 (24), 14903 (2020).[7] E. Bestelink, et al., Adv. Electron. Mater., 9, 2201163 (2023).[8] E. Bestelink, et al., Adv. Opt. Mater., 2301931 (2023).[9] E. Bestelink, et al., J. Mater. Chem. C, 11, 11688 (2023).[10] E. Bestelink, et al., Adv. Electron. Mater., 8, 2101101 (2021).[11] E. Bestelink, et al., Adv. Itell. Sys., 3, 2000199 (2021). Figure 1

22‐2: Significant Improvement of a‐IGZO Source‐Gated Transistor Current over Traditional Design through Architecture Modification

We introduce a new architecture, alternative double work function (a‐DWF), device to dramatically enhance the output current of source gated transistors (SGT) while retaining low voltage saturation. The smaller output current of SGT and previous DWF devices compared to conventional thin‐film transistors (TFT) has previously limited their application range.

Toward low-power-consumption source-gated phototransistor

The power consumption is challenging the next-generation electronic and optoelectronic devices. In this Letter, the n-type source-gated transistor (SGT) enabled by CdS nanobelt is investigated in detail, demonstrating the expected low power consumption, along with impressive photodetection performance. The SGT is realized by deliberately introducing the Schottky barrier at the source of the staggered-electrode transistor, exhibiting a small saturated voltage (VSAT) of 0.84 ± 0.21 V and a remarkably low power consumption of 7.56 ± 4.01 nW. Under illumination, the as-constructed SGT also shows a low power consumption of 7.58 nW, which is much lower than that of the most reported phototransistors operating in the saturated region. Moreover, the source-gated phototransistor also shows a high responsivity of 2.54 × 103 A W−1 and a high detectivity of 6.72 × 1012 Jones. All results imply that the as-constructed low-power-consumption source-gated phototransistor promises next-generation high-performance electronic and optoelectronic devices.

Promoting Low-Voltage Saturation in High-Performance a-InGaZnO Source-Gated Transistors

Promoting Low-Voltage Saturation in High-Performance a-InGaZnO Source-Gated Transistors

Organic Source‐Gated Phototransistors with > 104 Photo‐To‐Dark Current Ratio in the Visible Range at Zero Gate‐Source Bias

AbstractWith growing interest in organic phototransistors, as not only sensors but also neuromorphic computing elements, the vast majority of research investigates structures comprising Ohmic source/drain contacts. Here, it is shown how source‐gated transistors (SGTs), in which a source contact barrier dominates electrical characteristics, can be implemented as phototransistors. Organic photo‐SGTs (OPSGTs) based on vacuum‐processed small‐molecule dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐]thiophene (DNTT) demonstrate low saturation voltage, exceptional tolerance to channel length variation, and photo‐to‐dark current ratio (PDCR) peaks over 106 for 819 µW broad spectrum incident light power. At zero gate‐source voltage, the PDCR reaches 104, showing promise for simple sensor circuit implementation in medical and wellbeing applications.

Evidence of Improved Thermal Stability via Nanoscale Contact Engineering in IGZO Source-Gated Thin-Film Transistors

Despite rapidly expanding interest in thin-film source-gated transistors (SGTs), the high-temperature dependence of drain current (TDDC) in devices comprising Schottky source barriers is delaying wide adoption. To reduce this effect, alternative source designs have been theorized. Specifically, introducing additional nanoscale layers at the source contact should facilitate the tunneling of charge carriers at the Fermi energy level with negligible TDDC. Here, we fabricate amorphous In <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> Ga <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> ZnO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{7}}$</tex-math> </inline-formula> tunnel-contact SGTs (TC-SGTs) with three times lower TDDC than polysilicon transistors with Schottky contacts. Numerical simulations help elucidate the control mechanisms. We show that the potential profile across the semiconductor in the bulk of the source-gate overlap region determines injection current, and the introduction of a thin interfacial layer at the contact reduces the role of the contact metal work function (WF) in current control and associated temperature effects. This device architecture adds improved thermal stability to the long list of SGT benefits, including low voltage saturation, power-efficient operation, high intrinsic gain, device-to-device uniformity, and robustness to mechanical and electrical stress.

P‐6: Study of source‐gated transistor (SGT) for output current enhancement through TCAD simulation

Source‐gated transistor (SGT) proves to be a promising candidate as an alternative structure for displays. However, the on‐current of SGT is relatively low when compared with conventional thin‐film transistor structures. This research proposes a new structure with higher current while retaining SGT characteristics. This structure is suitable for low power and wearable devices.

Printed 700 V/V Gain Amplifiers Based on Organic Source‐Gated Transistors with Field Plates

AbstractPrinted amplifiers are promising components for flexible and wearable devices. The circuits need to have small footprint, high amplification, and low power consumption, which is not simultaneously possible with conventional thin‐film transistors because multiple stages are required and introduce sources of variability, failure, or wasted area. Source‐gated transistors (SGTs) can in principle have extremely high intrinsic gain but this is not always the case because of lateral field control problems. A good solution is the use of field plate structures, which are straightforward to implement with top contacts but not so with bottom contacts. Here, a printed implementation of organic SGT with a field plate is presented, which can achieve a record high intrinsic gain of 920 V/V. The single‐stage common‐source amplifier with two organic SGTs also exhibits a high gain of 700 V/V. Simulations confirm the effectiveness of the printed field plate, making it a promising approach for future flexible and wearable electronics.

High-Performance Organic Source-Gated Transistors Enabled by the Indium-Tin Oxide–Diketopyrrolopyrrole Polymer Interface

Source-gated transistors are a new driver of low-power high-gain thin-film electronics. However, source-gated transistors based on organic semiconductors are not widely investigated yet despite their potential for future display and sensor technologies. We report on the fabrication and modeling of high-performance organic source-gated transistors utilizing a critical junction formed between indium-tin oxide and diketopyrrolopyrrole polymer. This partially blocked hole-injection interface is shown to offer both a sufficient level of drain currents and a strong depletion effect necessary for source pinch-off. As a result, our transistors exhibit a set of outstanding metrics, including an intrinsic gain of 160 V/V, an output resistance of 4.6 GΩ, and a saturation coefficient of 0.2 at an operating voltage of 5 V. Drift-diffusion simulation is employed to reproduce and rationalize the experimental data. The modeling reveals that the effective contact length is significantly reduced in an interdigitated electrode geometry, eventually contributing to the realization of low-voltage saturation.

High-performance and low-power source-gated transistors enabled by a solution-processed metal oxide homojunction

Cost-effective fabrication of mechanically flexible low-power electronics is important for emerging applications including wearable electronics, artificial intelligence, and the Internet of Things. Here, solution-processed source-gated transistors (SGTs) with an unprecedented intrinsic gain of ~2,000, low saturation voltage of +0.8 ± 0.1 V, and a ~25.6 μW power consumption are realized using an indium oxide In2O3/In2O3:polyethylenimine (PEI) blend homojunction with Au contacts on Si/SiO2. Kelvin probe force microscopy confirms source-controlled operation of the SGT and reveals that PEI doping leads to more effective depletion of the reverse-biased Schottky contact source region. Furthermore, using a fluoride-doped AlOx gate dielectric, rigid (on a Si substrate) and flexible (on a polyimide substrate) SGTs were fabricated. These devices exhibit a low driving voltage of +2 V and power consumption of ~11.5 μW, yielding inverters with an outstanding voltage gain of >5,000. Furthermore, electrooculographic (EOG) signal monitoring can now be demonstrated using an SGT inverter, where a ~1.0 mV EOG signal is amplified to over 300 mV, indicating significant potential for applications in wearable medical sensing and human-computer interfacing.

High gain complementary inverters based on comparably-sized IGZO and DNTT source-gated transistors

Complementary inverters using IGZO n-channel and DNTT p-channel source-gated transistors are demonstrated for the first time. They exhibit gain of 368 V V−1, 94% noise margin and matching on-current for relatively similar widths.

Extraordinarily Weak Temperature Dependence of the Drain Current in Small‐Molecule Schottky‐Contact‐Controlled Transistors through Active‐Layer and Contact Interplay

AbstractLow saturation voltages and extremely high intrinsic gain can be achieved in contact‐controlled thin‐film transistors (TFTs) with staggered device architecture, enabled by the energy barrier introduced at the source contact. The resulting device, the source‐gated transistor (SGT), is limited in its usefulness by the high temperature dependence of the drain current induced by the source energy barrier. Here, the interaction between the thermal characteristics of the source contact and the semiconductor to show drastically reduced temperature dependence for SGTs based on organic semiconductors (OSGTs) is exploited. This extraordinarily weak temperature dependence of the drain current is observed regardless of the height of the source energy barrier (27.8% in OSGTs with Ti contacts compared to 22.1% when using Au contacts, over a 34 K range). The reduction in mobility of the semiconductor offsets an increase in thermionic‐field emission of charge carriers at the source. This is a first for SGTs and provides a route to removing one of the last hurdles to their wider adoption. The OSGTs with Ti contacts also demonstrate: drain‐current saturation at very low drain‐source voltages (saturation factor of 0.22); noteworthy stability after 70 days; and minimal drain‐current variation with channel length or illumination.

N-Type Printed Organic Source-Gated Transistors with High Intrinsic Gain.

Source-gated transistors (SGTs) are emerging devices enabling high-gain single-stage amplifiers with low complexity. To date, the p-type printed organic SGT (OSGT) has been developed and showed high gain and low power consumption. However, complementary OSGT circuits remained impossible because of the lack of n-type OSGTs. Here, we show the first n-type OSGTs, which are printed and have a high intrinsic gain over 40. A Schottky source contact is intentionally formed between an n-type organic semiconductor, poly{[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5'-(2,2'-bithiophene)} (N2200), and the silver electrode. In addition, a blocking layer at the edge of the source electrode plays an important role to improve the saturation characteristics and increase the intrinsic gain. Such n-type printed OSGTs and complementary circuits based on them are promising for flexible and wearable electronic devices such as for physiological and biochemical health monitoring.

New Approach to Low-Power-Consumption, High-Performance Photodetectors Enabled by Nanowire Source-Gated Transistors.

Power consumption makes next-generation large-scale photodetection challenging. In this work, the source-gated transistor (SGT) is adopted first as a photodetector, demonstrating the expected low power consumption and high photodetection performance. The SGT is constructed by the functional sulfur-rich shelled GeS nanowire (NW) and low-function metal, displaying a low saturated voltage of 0.61 V ± 0.29 V and an extremely low power consumption of 7.06 pW. When the as-constructed NW SGT is used as a photodetector, the maximum value of the power consumption is as low as 11.96 nW, which is far below that of the reported phototransistors working in the saturated region. Furthermore, benefiting from the adopted SGT device, the photodetector shows a high photovoltage of 6.6 × 10-1 V, a responsivity of 7.86 × 1012 V W-1, and a detectivity of 5.87 × 1013 Jones. Obviously, the low power consumption and excellent responsivity and detectivity enabled by NW SGT promise a new approach to next-generation, high-performance photodetection technology.

(Invited, Digital Presentation) Oxide TFTs Based on Semiconductors and Semimetals

Oxide semiconductors have opened a new era for large-area, flexible and transparent applications. Despite the progresses, a bottleneck issue of oxide thin-film transistors (TFTs) is the instability either under bias stress or when used as a current source. Furthermore, the carrier mobility and current driving capability need to be improved for high-spec displays. It is still hugely challenging to overcome both issues using the conventional device structure and oxide semiconductor materials.Here, we review our recent work on novel oxide TFTs that show a few desirable properties. Rather than using an ohmic metal contact as the source electrode, a high work-function Schottky source contact enables depletion around the TFT source region, which results in intrinsic immunity to the negative bias illumination stress, no obvious short channel effect, and superb current saturation over a wide range of drain voltage1. The flat saturation current gives rise to an extremely high voltage gain reaching 23,000, which is, to the best of our knowledge, the highest gain ever achieved by a solid-state transistor to date. The threshold voltage is also found to remain stable under different drain voltages, in contrast to standard TFTs, which may be useful in larger-area displays where the drain voltages of the drive TFTs can differ2. Furthermore, the depletion provided by the Schottky source electrode allows utilizing semi-metal ITO to replace IGZO as the TFT channel layer, which significantly enhances the carrier mobility and current driving capability. Other related work may also be discussed in the talk including oxide Schottky diodes operating beyond 10 GHz3, oxide TFTs operating beyond 1 GHz4, significantly enhanced carrier mobility by self-assembled monolayer treatment5,6, and CMOS-like oxide-based logic circuits7,8. References Extremely high-gain source-gated transistors, J Zhang, J Wilson, G Auton, Y Wang, M Xu, Q Xin, A Song, Proceedings of the National Academy of Sciences 116 (11), 4843-4848 (2019)Comparative Study of Short-Channel Effects Between Source-Gated Transistors and Standard Thin-Film Transistors, Zhenze Wang, Li Luo, Yiming Wang, Jiawei Zhang, and Aimin Song, IEEE Transactions on Electron Devices, 69(2), 561 - 566 (2022).Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz, J Zhang, Y Li, B Zhang, H Wang, Q Xin, A Song, Nature communications 6 (1), 1-7 (2015).Amorphous-InGaZnO thin-film transistors operating beyond 1 GHz achieved by optimizing the channel and gate dimensions, Y Wang, J Yang, H Wang, J Zhang, H Li, G Zhu, Y Shi, Y Li, Q Wang, Qian Xin, Zhongchao Fan, Fuhua Yang, Aimin Song, IEEE Transactions on Electron Devices 65 (4), 1377-1382 (2018).Significant Performance Improvement of Oxide Thin‐Film Transistors by a Self‐Assembled Monolayer Treatment, W Cai, J Zhang, J Wilson, J Brownless, S Park, L Majewski, A Song, Advanced Electronic Materials 6 (5), 1901421 (2020).Significant performance enhancement of very thin InGaZnO thin-film transistors by a self-assembled monolayer treatment, W Cai, J Wilson, J Zhang, J Brownless, X Zhang, LA Majewski, A Song, ACS Applied Electronic Materials 2 (1), 301-308 (2020).Complementary integrated circuits based on p-type SnO and n-type IGZO thin-film transistors, Y Li, J Yang, Y Wang, P Ma, Y Yuan, J Zhang, Z Lin, L Zhou, Q Xin, Aimin Song, IEEE Electron Device Letters 39 (2), 208-211 (2017).Thin Film Sequential Circuits: Flip-Flops and a Counter Based on p-SnO and n-InGaZnO, Y Yuan, J Yang, Y Wang, Z Hu, L Zhou, Q Xin, A Song, IEEE Electron Device Letters 42 (1), 62-65 (2020).

Polymer source-gated transistors with low saturation voltage

High ionisation potential polymer transistors with unavoidable Schottky contacts are used to provide very stable and low-current operation with a very low saturation voltage of 2 V even with thick gate dielectric due to source-gated transistor design.

Contact Doping as a Design Strategy for Compact TFT-Based Temperature Sensing

Contact-controlled devices, such as source-gated transistors (SGTs), deliberately use energy barriers at the source, and naturally, the positive temperature dependence (PTD) of drain current can be utilized for temperature sensing. We exploit the difference in drain current activation energy, which arises with contact doping in polysilicon n-type contact-controlled transistors, to demonstrate output current with either a PTD or negative temperature dependence (NTD). The range over which output current varies linearly with temperature, as well as the sensitivity, can be tailored by the choice of reference current magnitude and relative source contact properties within the current mirror. The sensing scheme simplifies the circuit design because it relies solely on thin-film transistors and it has inherent immunity to output voltage variation. This ability to tune the sign of temperature dependence allows facile integration in applications requiring homeostasis via feedback, e.g., electronic skin, in a minimal layout area and potentially with convenient reduction of patterning steps during fabrication.

New Opportunities for High-Performance Source-Gated Transistors Using Unconventional Materials.

Source‐gated transistors (SGTs), which are typically realized by introducing a source barrier in staggered thin‐film transistors (TFTs), exhibit many advantages over conventional TFTs, including ultrahigh gain, lower power consumption, higher bias stress stability, immunity to short‐channel effects, and greater tolerance to geometric variations. These properties make SGTs promising candidates for readily fabricated displays, biomedical sensors, and wearable electronics for the Internet of Things, where low power dissipation, high performance, and efficient, low‐cost manufacturability are essential. In this review, the general aspects of SGT structure, fabrication, and operation mechanisms are first discussed, followed by a detailed property comparison with conventional TFTs. Next, advances in high‐performance SGTs based on silicon are first discussed, followed by recent advances in emerging metal oxides, organic semiconductors, and 2D materials, which are individually discussed, followed by promising applications that can be uniquely realized by SGTs and their circuitry. Lastly, this review concludes with challenges and outlook overview.

Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors

Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore's law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor's unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a two-transistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing

We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1].The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5].SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance gd [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising gd . While gd is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1].Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps.The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low gd are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.Figure. 1 a) Photomicrograph of a µ-Si floating gate MMT (FG MMT); b) FG2 potential is significantly raised, while FG1 is shielded from parasitic capacitive coupling from the channel and drain potential, keeping charge injection at the source constant with drain voltage. c) Output conductance gd comparison confirms FG MMT gd is significantly lower than that of the equivalent FG SGT.