Source Follower Amplifier Research Articles

A Cryogenic Front-End Preamplifier Operating at 120 K for Bolometric Detector

In this paper, the design and test results of a front-end cryogenic amplifier for a bolometer detector are presented. The amplifier is implemented with two low-noise Si JFETs, where the first FET is configured as a source follower amplifier and the second FET provides a high dynamic resistance to keep the voltage gain very close to unity. A 3 dB bandwidth over a wide range from DC to 10 MHz is achieved in this design. The input voltage noise density is ~ 1.9 nV/√Hz at 300 K, which further reduces to 1.6 nV/√Hz at 120 K. The flicker corner frequency observed is below 50 Hz.

A CMOS slew-rate enhanced OTA for imaging

CMOS Image Sensors have many applications currently. They are present everywhere and almost everyone owns many cameras based on these sensors ranging from mobile phones (with several cameras), to tablets, computers, security devices and cars. Although they work pretty well as we increase their resolution and quality we face a few problems. One of these problems is Flicker noise. The other source of noise, thermal, evolved a lot recently and flicker noise is now the main limitation regarding improving the performance. This work presents a new method to reduce the flicker noise contribution in the overall sensor noise by reducing the time for Double Sampling, allowing to filters more correctly the flicker noise spectrum introduced by the pixel source follower amplifier. We also introduce a way to remove the column induced lag that comes from the column readout circuitry by using strong and stable references. We propose a new amplifier that is used as a buffer for the reference voltage. At the same time Double Sampling is performed. This solution contributes both to reduce the current consumption and time between samples which also contributes to a lower power heat dissipation. The developed circuit can be seen as a generic solution for applications that need stable references and high resolution, resulting in a massively parallel circuit, as it is common in CMOS image sensors. The proposed solution is tested with a circuit containing 3000 readout columns.

TCAD simulation of a single Monolithic Active Pixel Sensors based on High Voltage CMOS technology

ABSTRACTA model of a High Voltage CMOS (HV-CMOS) Monolithic Active Pixel Sensor (MAPS) has been modelled using Technology Computer Aided Design (TCAD). The model has incorporated both the active region and the on-pixel readout circuits which were comprised of a source follower amplifier and an integrated charge amplifier. The simulation has examined the electrical characteristics and response output of a HV-CMOS MAPS sensor using typical dimensions, levels of doping in the structural layers and bias conditions for this sensor. The performance of two alternate designs of amplifier have been examined as a function of the operating parameters. The response of the sensor to the incidence of Minimum Ionizing Particles (MIPs) at different energies has been included in the model.

A Low Dark Leakage Current High-Sensitivity CMOS Image Sensor With STI-Less Shared Pixel Design

A CMOS image sensor with a low dark current and high sensitivity is developed with shallow trench isolation (STI) less shared pixel. By sharing in-pixel transistors, such as the reset transistor, select transistor, and source follower amplifier, each pixel achieves a high fill factor of 43% and a high sensitivity of 144.6 ke <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /lx · s. In addition, compared with a conventional image sensor which has the STI structure in the pixel for isolation, the developed image sensor achieves a relatively low dark current of 104.5 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /s/pixel (median), corresponding to a current density J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dark</sub> of approximately 30 pA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 60 °C. This is a low value and the consequence of not using STI as pixel isolation. Both types of pixels, namely the conventional and the proposed active pixel sensor have the same pixel size of 7.5 × 7.5 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and are fabricated by the same process. The developed imager with STI-less shared pixel obtains sufficiently good responses at 400 to 900 nm, and, particularly, a peak QE of 68% at 600 nm. This is suitable for scientific applications.

A CMOS image sensor using column-parallel forward noise-canceling circuitry

In this paper, a new column-parallel analog readout architecture, which is composed of a high-gain amplifier, a forward noise-canceling circuitry (FNC), and sample-and-hold (S/H) capacitors, has been presented for low-noise CMOS image sensors (CIS). A FNC has been proposed to provide a sharp noise-filtering for high-frequency noise arising from the readout signal chain, which effectively reduces random noise of the pixel source follower and column amplifier. In order to keep the high-sensitivity and high-dynamic range output, dual-gain readout chains have been adopted. A prototype 400H × 250V CIS using the readout architecture with the FNC was fabricated in a 0.18 µm 1-poly 3-metal CMOS process with pinned-photodiodes. The experimental results revealed the input-referred noise of the proposed readout architecture was 65 µVrms, which has been reduced by 24% compared to that of the conventional readout architecture.

A Low Noise Wide Dynamic Range CMOS Image Sensor With Low-Noise Transistors and 17b Column-Parallel ADCs

An extremely low temporal noise and wide dynamic range CMOS image sensor is developed using low-noise transistors and high gray-scale resolution (17b) folding-integration/cyclic analog-to-digital converter (ADC). Two types of pixel are designed. One is a high conversion gain (HCG) pixel with removing the coupling capacitance between the transfer gate and the floating diffusion, and the other is a pixel for wide dynamic range (WDR) CMOS imager with a native transistor as a source follower amplifier. The CMOS image sensor that is in combination with the proposed pixels and the high performance column ADC has achieved a low pixel temporal noise of 1.1e <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> , a wide dynamic range of 87.5 dB with the video rate operation (30 Hz) and the vertical fixed pattern noise of 1.08-μVrms. The implemented HCG CMOS imager and WDR CMOS imager using 0.18 μm technology have the pixel conversion gain of 73.2- and 22.8-μV/e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> , respectively.

Simple and low‐cost tracking generator design in envelope tracking radio frequency power amplifier system for WCDMA applications

A simple analogue technique called auxiliary envelope tracking, or AET, is presented, which is shown to be capable of improving the efficiency of a radio frequency power amplifier (RFPA). This AET signal is an amplified envelope signal that supplies the drain port of the RFPA. The concept of AET is explained and a theoretical background for the technique is presented. The main feature of this technique lies in the separation of the DC and AC components of the tracking signal. This allows for a very simple and low-cost tracking generator design that consists of a simple source follower amplifier and an RF broadband transformer. A practical system has been implemented and the measured results are obtained for WCDMA signals. A measurement on the realised system shows a 50% improvement in the drain efficiency at average output power of 33 dBm of a 25 W GaN. This substantial improvement is achieved at a competitive WCDMA signal with peak-to-average envelope power ratio of 9.17 dB.

RTS noise reduction of CMOS image sensors using amplifier-selection pixels

This paper describes a RTS (random telegraph signal) noise reduction technique for an active pixel CMOS image sensor (CIS) with in-pixel selectable dual source-follower amplifiers. In this CMOS image sensor, the lower-noise transistor in each pixel is selected in the readout operation using a table of determining the lower-noise transistors of all the pixels. A prototype image sensor with 65×290 pixels for demonstrating the effectiveness of this technique has been implemented using 0.18µm CMOS image sensor technology with pinned photodiode option. The measured result shows that the maximum noise using the amplifier-selection technique is reduced to 9.6e- from 17.2e- which is the maximum noise of the image array using one of two amplifiers in each pixel without selection.

A Flexible Front-End Signal Processor for High-Speed Image Sensor Readout

Abstract The High-Speed Image Pre-Processor with Oversampling (HIPPO) is a prototype image sensor readout integrated circuit designed for both high performance and enhanced flexibility. HIPPO's initial target application is the instrumentation of bufferless, column-parallel, soft x-ray Charge-Coupled Device (CCD) image sensors operating at column rates up to 10 MHz, enabling 10,000 frames-per-second (fps) video rates. HIPPO's architecture is flexible and allows design tradeoffs between speed, accuracy, and area. This architectural flexibility will enable the fast development of related image sensor and particle detector readout ICs based on HIPPO technology. HIPPO contains 16 channels, each comprising a charge amplifier, a dual-slope correlated double sampler, a sample-and-hold, a multiplexed 12b, 80 MS/s pipelined ADC (one ADC for every 4 channels), and a 480 Mb/s output serializer. HIPPO achieves 35 e-read noise at 10,000 fps for a 1 Mpixel sensor, improving to 24 e-at 5000 fps. HIPPO's charge-domain input obviates the source follower amplifier used in most CCDs and enables the implementation of a fully column-parallel CCD architecture. HIPPO was specifically designed to be flexible in both the sequencing of its operations and in its ability to accommodate input rates potentially varying over an order of magnitude.

A Dynamic Source-Follower Integrator and Its Application to .DELTA..SIGMA. Modulators

A switched-capacitor integrator based on dynamic source follower amplifiers has been proposed. Integrator operation has been confirmed and analyzed by assuming 0.18-µm CMOS technology. The integrator can reduce the number of elements considerably compared with conventional ones using operational amplifiers. As a result, the power dissipation of proposed integrator can be reduced to approximately one-eighth that of conventional integrators. The integrator is applied to a second-order ΔΣ modulator, and its successful operation has been confirmed by transistor-level circuit simulation.

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS

This brief presents the design and implementation of a high-speed and high-accuracy power-switchable track-and-hold (T/H) in 90-nm CMOS that achieves a total harmonic distortion of - 60 dB at 100 MS/s. With the proposed power-switching (P-S) technique, the T/H amplifier obtains not only further power optimization but also enhanced sampling speed and accuracy. The P-S technique requires no extra voltage headroom in the source-follower amplifier, thus allowing a relatively large input voltage swing of 0.8-Vpp in differential mode. A spurious-free dynamic range of 70 dB at 100 MS/s was measured with an input of 40.6 MHz and 0.8 Vpp. While driving a 2.5-pF capacitive load, the T/H consumes 2.97 mW from the 1.2-V supply.

A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

A low-power pipelined ADC featuring dynamic source follower amplifiers is presented in this paper. The proposed dynamic source follower-based architecture provides a low-power alternative to the traditional opamp-based MDAC circuits. This new type of circuit dynamically charges its load capacitance without a large bias current, leading to significant power savings. The presented ADC includes a low-power comparator with offset calibration and uses digital calibration for gain correction. Measured results indicate that the 9.4-bit, 50-MS/s prototype ADC achieves an SNDR of 49.2 dB (7.9 ENOB) and consumes 1.44 mW from a 1.2-V supply, resulting in a figure of merit of 119 fJ/conversion-step. The converter's input capacitance is 90 fF and the total active area is 0.123 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 90 nm CMOS process.

Impact of Substrate Bias on Fixed-Pattern-Noise in Active Pixel Sensor Cells

The effect of substrate (body) bias on fixed-pattern-noise (FPN) in active pixel sensor (APS) cells is studied. Through measuring test devices consisting of two metal–oxide–semiconductor field-effect transistors (MOSFETs) connected in series with each of the transistors located in the same well region, it has been revealed that substrate bias, which is inevitably applied in a normal circuit configuration in conventional APS cells, worsens the characteristics fluctuation in source-follower amplifiers in APS cells, leading to FPN that cannot be mitigated by conventional correction methods such as correlated double sampling. In addition it has been confirmed that the current–voltage characteristics of logarithmic converters, each of which is realized using a MOSFET with gate and drain terminals connected together, are also affected by substrate bias, resulting in increased characteristics fluctuation as compared with the case with no substrate bias.

Process Optimization for Monolithic Integration of Piezoresistive Pressure Sensor and MOSFET Amplifier with SOI Approach

In this paper we present the design and process optimization for fabricating piezoresitive pressure sensor and MOSFET Differential Amplifier simultaneously on the same chip. Silicon On Insulator approach has been used for realizing the membrane as well as the electronics on the same chip. The amplifier circuit has been configured in the common source connection and it has been designed with PSPICE simulation to achieve a voltage gain of about 5. In the initial set of experiments the Pressure sensor and the amplifier were fabricated on separate chips to optimize the process steps and tested in the hybrid mode. In the next set of experiments, SOI wafer having the SOI layer thickness of about 11 microns was used for realizing the membrane by anisotropic etching from the backside. The piezo-resistive pressure sensor was realized on this membrane by connecting the polysilicon resistors in the form of a Wheatstone bridge. The MOSFET source follower amplifier was also fabricated on the same SOI wafer by tailoring the process steps to suit the requirement of simultaneous fabrication of piezoresistors and the amplifier for achieving MOSFET Integrated Pressure Sensor. Reproducible results have been achieved on the SOI wafers, with the process steps developed in the laboratory. Sensitivity of 270 mV /Bar/10V, with the on chip amplifier gain of 4.5, has been achieved with this process.

New materials and processes for flat panel X-ray detectors

Flat panel X-ray imagers using amorphous silicon active matrix addressing have been introduced to the medical imaging market at sizes up to 40×40 cm and with up to 10 million pixels. Some new technology developments, which can further increase the performance of these devices, are described. High atomic number polycrystalline X-ray photoconductors can operate near the theoretical sensitivity and at reasonably low bias voltages. The higher sensitivity obtained in HgI2 allows single-photon detection, which opens up new imaging opportunities. Another approach to improve sensitivity is to integrate an amplifier at the pixel level, which requires laser-recrystallised polysilicon transistors. A pixel-level source follower amplifier is shown to have enough gain to overcome other noise sources. A three-dimensional device structure is needed to accommodate the pixel electronics, and so the sensor is deposited on top of the electronics, separated by a thick passivation layer. Future possible detector technologies based on printing and organic semiconductors are discussed.

A 1/2-in 1.3 M-pixel progressive-scan IT-CCD for digital still camera applications

A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progressive-scan IT-CCD (8.3/spl times/7.1 mm/sup 2/) for the SXGA format. A two-phase-drive horizontal-CCD with phosphorus-implanted storage regions helps reduce the driving voltage to 2.5 V, resulting in the power consumption of the device being as low as 146 mW. A new source-follower amplifier with separate p-well driver transistors achieves 12% higher gain than that obtained using a conventional amplifier. An overflow drain with a self-adjusting potential barrier can instantly remove superfluous charges in vertical-CCDs just before an exposure period, which enables DSCs to perform such functions as quick auto-focusing and dark-current removal. New dual operation modes for still and motion pictures can provide not only high-resolution color signals in a 15-frame/s 1050-line progressive mode but also wide-dynamic-range color signals in a 30-frame/s 525-line progressive mode. The latter mode employs a pixel-exchange-and-mix readout operation that helps halve the number of scanning lines with no loss in sensitivity and color information.

Noise characteristic design of CMOS source follower and voltage amplifier for active semiconductor micro-electrodes for neural signal recording.

A noise performance design method for the pre-amplifiers of an active neural probe is given. The on-chip circuitry of the active neural probe consists of CMOS devices that show high-/low-frequency noise, so that the device noise can become dominant. Analysis of the signal-to-device-noise ratio (SDNR) for the CMOS source follower buffer and two-stage differential voltage amplifier is given. Closed-form expressions for the output noise power are derived and exploited to tailor the parameters that are controllable during circuit design. The output SDNR is calculated considering the real extracellular action potentials, the electrode-electrolyte interface and the noise spectrum of CMOS devices from typical foundries. It is shown that the output device noise power can be much higher than the output signal power if the devices at the input stage of the pre-amplifier are made as small as given fabrication technology permits. Quantitative information of the circuit parameters to achieve an SDNR higher than 5 for neural spikes with 60 microV amplitude are provided for both pre-amplifier types.

A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing 0.25-μm gap single-layer poly-Si electrodes

A 1/2-in, 1.3 M-pixel progressive-scan interline-transfer charge coupled-device (IT-CCD) image sensor has been developed for low-power and high-sensitivity digital cameras. The image sensor uses 0.25-/spl mu/m gap single-layer poly-Si for CCD transfer electrodes in order to reduce the power consumption and number of fabrication process steps. The image sensor achieved a low driving voltage (2.1 V) on a horizontal CCD (H-CCD) at a frequency of 24.5 MHz. An original pixel layout and a self-aligned photodiode structure make it possible to achieve a progressive scan pixel with well-controlled photodiode readout characteristics. An output three-stage source follower amplifier with new multioxide transistors, whose gate insulator thickness is thinner than that of a CCD register, is able to attain 17% higher gain than that of the conventional amplifier. The sensor provides low-power (100 mW) and high output sensitivity. The total number of steps for fabricating the sensor was reduced to 70% of that for conventional three-layer poly-Si electrodes.

固体撮像とその関連技術 １６０万画素増幅型イメージセンサＢＣＡＳＴの開発

This paper introduces a new device architecture suitable for obtaining a large format, high resolution, and high performance image sensor. Each pixel in the sensor comprises a buried photodiode and a junction field effect transistor, for signal charge generation and amplificaion, respectively. A 1.6 M pixel image sensor was constructed with source follower amplifiers and correlated double sampling circuits for signal readout. The image sensor exhibited high-sensitivity, low-noise, and high-protection capabilities for blooming and smear. The fundamental characteristics-sensitivity of 2 V/lx·s, dynamic range of 75 dB, noise equivalent exposure of 9.2×10-5lx·s, and a dark FPN level of -66 dB were achieved.

Source follower or charge amplifier? An experimental comparison using a detector with integrated electronics

In spectroscopy systems where the front-end amplifier is an external circuit, charge sensitive preamplifiers have been shown to be superior in performance with respect to voltage amplifiers as the first stage of amplification. The paper studies how these two circuit configurations behave when they are integrated in high resolution semiconductor detectors of very small capacitance. This paper for the first time compares, in this new condition, the stability of amplification of the source follower with the optimum behavior of the charge preamplifier, reporting its dependence on the detector bias, on the input transistor bias, and on the operating temperature. This paper then discusses the consequent loss in linearity and resolution that a system with an integrated source follower may undergo depending on the type of reset mechanism. The point of how the instabilities of the integrated feedback capacitance limit the performance of an integrated charge amplifier is also addressed. The analysis is based on experimental results obtained with the same detector with integrated electronics used in the two different configurations.