Solid State Disks Research Articles

Experimental Study of Data Transmission Efficiency on a Solid State Disk within a Vibrating Situation

Because of the high sensitivity of data transmission when impacted externally, vibration control on a hard disk becomes crucial. In order to investigate the influence of data transmission with respect to the tilted angle of a solid state disk (SSD) and the hardness of the damping material, a series of experimental tests using a base-excitation vibrating system in conjunction with data transmission measuring software (IOmeter software) as well as an acceleration meter is adopted. In addition, to initialize the difference of the data transmission between the SSD and a traditional hard disk (HD), a series of tests for the HD that adjust the tilted angle and hardness of the damping material is also carried out. Moreover, to understand the influence of data transmission with respect to the warming-up process, a data transmission before and after adding the warming-up process is employed. Results reveal that data transmission efficiency can be improved if the damping material is added within the SSD and the HD. Also, the data transmission efficiency of a 0° tilted angle is better than that of a 5° or 10° tilted angle. Furthermore, the data transmission efficiency of the SSD is superior to that of the HD. Consequently, data transmission efficiency will be tremendously improved after the SSD is warmed-up.

Descrambling data on solid-state disks by reverse-engineering the firmware

Data recovery is an important component of digital forensic research. Although recovering data from hard drives or small-scale mobile devices has been well studied, solid-state disks (SSDs) have a very different internal architecture and some additional functions, and it is not clear whether these differences will have an effect on data recovery. Data scrambling is an additional function of an SSD controller which can improve data reliability, but makes data recovery difficult. In this research, the dedicated flash software was first introduced that can acquire the physical image of an SSD without destroying the device hardware. Based on the software, a validation experiment was presented to evaluate the effect of data scrambling on data recovery and the causes of the effect were analyzed. Then two approaches to descrambling the data in the flash chips were proposed and their advantages and disadvantages discussed. After that, a procedure to identify the scrambling seeds that are used to descramble the scrambled data was described. Finally, descrambling software was implemented based on the second descrambling method. The experiment shows that this software can successfully descramble the data from an SSD flash drive regardless of the internal structure of the scrambler in the SSD controller and can generate an unscrambled physical image on which most existing data-recovery techniques can be effective.

Plugging Versus Logging

A promising technique to improve the write performance of solid-state disks (SSDs) is to use a disk write buffer. The goals of a write buffer is not only to reduce the write traffic to the flash chips but also to convert host write patterns into long and sequential write bursts. This study proposes a new buffer design consisting of a replacement policy and a write-back policy. The buffer monitors how the host workload stresses the flash translation layer upon garbage collection. This is used to dynamically adjust its replacement and write-back strategies for a good balance between write sequentiality and write randomness. When the garbage collection overhead is low, the write buffer favors high write sequentiality over low write randomness. When the flash translation layer observes a high overhead of garbage collection, the write buffer favors low write randomness over high write sequentiality. The proposed buffer design outperformed existing approaches by up to 20% under various workloads and flash translation algorithms, as will be shown in experiment results.

KMC 2: fast and resource-frugal k-mer counting.

Building the histogram of occurrences of every k-symbol long substring of nucleotide data is a standard step in many bioinformatics applications, known under the name of k-mer counting. Its applications include developing de Bruijn graph genome assemblers, fast multiple sequence alignment and repeat detection. The tremendous amounts of NGS data require fast algorithms for k-mer counting, preferably using moderate amounts of memory. We present a novel method for k-mer counting, on large datasets about twice faster than the strongest competitors (Jellyfish 2, KMC 1), using about 12 GB (or less) of RAM. Our disk-based method bears some resemblance to MSPKmerCounter, yet replacing the original minimizers with signatures (a carefully selected subset of all minimizers) and using (k, x)-mers allows to significantly reduce the I/O and a highly parallel overall architecture allows to achieve unprecedented processing speeds. For example, KMC 2 counts the 28-mers of a human reads collection with 44-fold coverage (106 GB of compressed size) in about 20 min, on a 6-core Intel i7 PC with an solid-state disk.

Efficient SSD Integrity Verification Program Based on Combinatorial Group Theory

In digital forensics, the issue of data integrity protection for increasingly widespread applied SSD (Solid State Disk, SSD) is to be resolved. Based on Combinatorial Group Theory, mapping data objects in SSD validation process and test object in combination group testing methods, using the non-adaptive mode to the initial calculation, stored procedures, and re-calculate, verify process, and carefully selecting the design parameters to construct the test matrix of Combinatorial Group Testing method in response to different application environments, we design testing group. The algorithm capabilities meet the requirements and that is higher efficiently by repeated tests. It is feasible for SSD integrity check based on the Combinatorial Group Theory.

Predictive Prefetching for Parallel Hybrid Storage Systems

In this paper, we present a predictive prefetching mechanism that is based on probability graph approach to perform prefetching between different levels in a parallel hybrid storage system. The fundamental concept of our approach is to invoke parallel hybrid storage system’s parallelism and prefetch data among multiple storage levels (e.g. solid state disks, and hard disk drives) in parallel with the application’s on-demand I/O reading requests. In this study, we show that a predictive prefetching across multiple storage levels is an efficient technique for placing near future needed data blocks in the uppermost levels near the application. Our PPHSS approach extends previous ideas of predictive prefetching in two ways: (1) our approach reduces applications’ execution elapsed time by keeping data blocks that are predicted to be accessed in the near future cached in the uppermost level; (2) we propose a parallel data fetching scheme in which multiple fetching mechanisms (i.e. predictive prefetching and application’s on-demand data requests) can work in parallel; where the first one fetches data blocks among the different levels of the hybrid storage systems (i.e. low-level (slow) to high-level (fast) storage devices) and the other one fetches the data from the storage system to the application. Our PPHSS strategy integrated with the predictive prefetching mechanism significantly reduces overall I/O access time in a hybrid storage system. Finally, we developed a simulator to evaluate the performance of the proposed predictive prefetching scheme in the context of hybrid storage systems. Our results show that our PPHSS can improve system performance by 4% across real-world I/O traces without the need of using large size caches.

Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks

Compared with either block or page-mapping Flash Translation Layer (FTL), hybrid-mapping FTL for flash Solid State Disks (SSDs), such as Fully Associative Section Translation (FAST), has relatively high space efficiency because of its smaller mapping table than the latter and higher flexibility than the former. As a result, hybrid-mapping FTL has become the most commonly used scheme in SSDs. But the hybrid-mapping FTL incurs a large number of costly full-merge operations. Thus, a critical challenge to hybrid-mapping FTL is how to reduce the cost of full-merge operations and improve partial merge operations and switch operations. In this article, we propose a novel FTL scheme, called Virtual Block-based Parallel FAST (VBP-FAST), that divides flash area into Virtual Blocks (VBlocks) and Physical Blocks (PBlocks) where VBlocks are used to fully exploit channel-level, die-level, and plane-level parallelism of flash. Leveraging these three levels of parallelism, the cost of full merge in VBP-FAST is significantly reduced from that of FAST. In the meantime, VBP-FAST uses PBlocks to retain the advantages of partial merge and switch operations. Our extensive trace-driven simulation results show that VBP-FAST speeds up FAST by a factor of 5.3--8.4 for random workloads and of 1.7 for sequential workloads with channel-level, die-level, and plane-level parallelism of 8, 2, and 2 (i.e., eight channels, two dies, and two planes).

A feedback-based adaptive data migration method for hybrid storage VOD caching systems

Nowadays Video-On-Demand (VOD) caching systems are often equipped with hybrid storage devices, which have been designed to combine the high read speed of Solid State Disks (SSDs) and the large capacity of Hard Disk Drives (HDDs). However, the number of erase cycles of SSDs is limited. So it is important to control the write load of SSDs in real applications. This paper proposes a Feedback-based Adaptive Data Migration (FADM) method, which can utilize the real-time feedback of the write load of SSDs to adjust the rule of moving data between HDDs and SSDs. More specifically, a video in HDDs is allowed to be moved into SSDs when its popularity is higher than that of the least popular video in SSDs by a threshold. This threshold is adaptively adjusted according to the feedback of the write load of SSDs. With FADM, the desired lifetime of SSDs can be well guaranteed even under various user behaviors while good read performance can be maintained. Simulations are done to demonstrate the effectiveness of FADM.

FLAP: Flash-aware Prefetching for Improving SSD-based Disk Cache

In modern enterprise storage systems, there is a trend that using NAND flash based solid state disks (SSDs) as a second-level disk cache to reduce the slow access to hard disk drives (HDDs) by caching the hot data of HDDs with SSDs. However, using SSDs for both caching and prefetching has rarely been discussed due to the performance penalty caused by unsuccessful prefetching, including garbage collection cost and disk bandwidth wasting. In this paper, a FLash-Aware Prefetching (FLAP) scheme has been presented to provide aggressive prefetching for improving the performance of sequential disk accesses. FLAP has been evaluated using well known real-world workloads. Experiment results show that FLAP can offer performance improvement under sequential workloads compared with pure caching, while reducing the internal garbage collection of SSDs

Using FPGA to Accelerate Deduplication on High-Performance SSD

Data deduplication technology applied in solid state disks (SSD), can reduce the amount of write operations and garbage collection, and thus improve writing performance and prolong lifetime. With the significant increase of write performance onto SSD, whether deduplication based on SSD could be a performance bottleneck of SSD comes to a spot worthy of our attention. To this end, this paper, firstly, performs an experiment on achieving deduplication via software method, and reveals that software-based deduplication decreases SSD's read and write performance. And then a hardware-based deduplication with details is proposed and implemented to accelerate deduplication using FPGA, and expected results are achieved. Finally, we come to the conclusion that hardware-based deduplication can not only guarantee read and write performance of SSD, but also save storage capacity and enhance endurance.

BF-tree

The increasing volume of time-based generated data and the shift in storage technologies suggest that we might need to reconsider indexing. Several workloads - like social and service monitoring - often include attributes with implicit clustering because of their time-dependent nature. In addition, solid state disks (SSD) (using flash or other low-level technologies) emerge as viable competitors of hard disk drives (HDD). Capacity and access times of storage devices create a trade-off between SSD and HDD. Slow random accesses in HDD have been replaced by efficient random accesses in SSD, but their available capacity is one or more orders of magnitude more expensive than the one of HDD. Indexing, however, is designed assuming HDD as secondary storage, thus minimizing random accesses at the expense of capacity. Indexing data using SSD as secondary storage requires treating capacity as a scarce resource. To this end, we introduce approximate tree indexing, which employs probabilistic data structures (Bloom filters) to trade accuracy for size and produce smaller, yet powerful, tree indexes, which we name Bloom filter trees (BF-Trees). BF-Trees exploit pre-existing data ordering or partitioning to offer competitive search performance. We demonstrate, both by an analytical study and by experimental results, that by using workload knowledge and reducing indexing accuracy up to some extent, we can save substantially on capacity when indexing on ordered or partitioned attributes. In particular, in experiments with a synthetic workload, approximate indexing offers 2.22x-48x smaller index footprint with competitive response times, and in experiments with TPCH and a monitoring real-life dataset from an energy company, it offers 1.6x-4x smaller index footprint with competitive search times as well.

Overview of emerging nonvolatile memory technologies

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Schemes for Extending the Lifetime of SSD

The limited use lifetime is a significant drawback of the solid state disk (SSD). When the P/E cycles exceed the nominal endurance limit, the entire SSD is rendered non-functional as worn out. As the low endurance, the MLC Flash based SSD is not suitable used in lifetime-aware applications and the total-byte-written of conventional MLC SSD is much less than SLC SSD. In this paper, we proposed an Adaptively Level Adjusting Scheme to use the MLC Flash dynamically to storage different amount of data levels through the entire lifetime. The result shows that the MLC SSD adopting this method could be totally written 4.8X more data than conventional MLC SSD and 16.5% more than SLC SSD. Another simple method named Post Life Slavaging Scheme is also proposed to benefit from the post life of a MLC SSD. It can extend the real P/E endurance by 2X when the user capacity reduced to 92% of original cacapcity.

A Statistics-Based Data Placement Strategy for Hybrid Storage

Although hard disk drives have been popular over several decades, there still exists the deficiency because of their slow speeds and high power consumptions. By contrast, flash-based solid state disks exhibit good performance and low power consumption. However, the limited lifetimes become a fatal flaw of solid state disks. In order to take full advantage of hard disk drives and solid state disks, we design a hybrid storage system to make them work in a complementary manner. Further, we propose a data placement scheme for this system to determine the data placement on the underlying solid state disks or hard disk drives based on the data access statistics. Experiment results show that the lifetime of solid state disks and the response time of the system can be significantly improved compared with the alone storage media.

Exploring optimal combination of a file system and an I/O scheduler for underlying solid state disks

Performance and energy consumption of a solid state disk (SSD) highly depend on file systems and I/O schedulers in operating systems. To find an optimal combination of a file system and an I/O scheduler for SSDs, we use a metric called the aggregative indicator (AI), which is the ratio of SSD performance value (e.g., data transfer rate in MB/s or throughput in IOPS) to that of energy consumption for an SSD. This metric aims to evaluate SSD performance per energy consumption and to study the SSD which delivers high performance at low energy consumption in a combination of a file system and an I/O scheduler. We also propose a metric called Cemp to study the changes of energy consumption and mean performance for an Intel SSD (SSD-I) when it provides the largest AI, lowest power, and highest performance, respectively. Using Cemp, we attempt to find the combination of a file system and an I/O scheduler to make SSD-I deliver a smooth change in energy consumption. We employ Filebench as a workload generator to simulate a wide range of workloads (i.e., varmail, fileserver, and webserver), and explore optimal combinations of file systems and I/O schedulers (i.e., optimal values of AI) for tested SSDs under different workloads. Experimental results reveal that the proposed aggregative indicator is comprehensive for exploring the optimal combination of a file system and an I/O scheduler for SSDs, compared with an individual metric.

Simulation-based optimization of wear leveling for solid-state disk digital video recording

As solid-state disk drives (SSDs) become more popular, there is a motivation to use them for digital video recording (DVR), especially in mobile and handheld devices. However, the unique limitations of flash-memory technology, the underlying technology of SSDs, require careful consideration when attempting to implement DVR on a SSD. This work outlines a simulation-driven exploration of wearleveling techniques that, coupled with previous work in SSD DVR optimization, yields a comprehensive strategy for using SSDs to implement DVR.

NAND flash service lifetime estimate with recovery effect and retention time relaxation

A service life model of NAND flash and threshold voltage shift process is proposed to calculate the service life and endurance. The relationships among achievable program/erase (P/E) cycles, recovery time, bad block rate and storage time are analyzed. The achievable endurance and service life of a NAND flash are evaluated based on a flash cell degradation and recovery model by varying recovery time, badblock rate, and storage time. It is proposed to improve the service lifetime of solid state disk by both relaxing the bad block rate limitation and retention time while extending the recovery time. The results indicate that endurance can be improved by 17 times if the storage time guarantee is reduced from 10 a to 1 a with 105 s recovery time inserted between cycles.

Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID

In this paper, a partial parity cache and data cache management method is presented for reducing the parity updating cost of a solid-state disk (SSD) based redundant array of inexpensive disk (RAID) system, thereby which the input/output (I/O) performance of the RAID system can be improved. SSDs have many advantages compared to hard disk drives. However, it is not advisable to directly add SSDs into a RAID system because doing so will decrease the performance and the life-time of the SSDs. In the RAID-5 system, parity generation includes read and write operations to the SSDs. Whenever there is a new write request to the RAID, the related parity must be updated and written to the SSDs. Such frequent parity updates result in poor RAID performance and shortens the life-time of the SSDs. This paper combines the prior methods and the proposed efficient buffer management method with a data cache. The proposed method reduces the number of read and write operations for generating parities in the RAID system. Experimental results show that the I/O performance of the RAID-5 system can be improved by 76% by using the proposed method.

Access devices for 3D crosspoint memory

The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.

HIOS

Garbage collection (GC) and resource contention on I/O buses (channels) are among the critical bottlenecks in Solid State Disks (SSDs) that cannot be easily hidden. Most existing I/O scheduling algorithms in the host interface logic (HIL) of state-of-the-art SSDs are oblivious to such low-level performance bottlenecks in SSDs. As a result, SSDs may violate quality of service (QoS) requirements by not being able to meet the deadlines of I/O requests. In this paper, we propose a novel host interface I/O scheduler that is both GC-aware and QoS-aware. The proposed scheduler redistributes the GC overheads across non-critical I/O requests and reduces channel resource contention. Our experiments with workloads from various application domains reveal that the proposed scheduler reduces the standard deviation for latency over stateof- the-art I/O schedulers used in the HIL by 52.5%, and the worst-case latency by 86.6%. In addition, for I/O requests with sizes smaller than a superpage, our proposed scheduler avoids channel resource conflicts and reduces latency by 29.2% compared to the state-of-the-art